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data sheet v1.4 2012-07 microcontrollers 32-bit tc1767 32-bit single-chip microcontroller
edition 2012-07 published by infineon technologies ag 81726 munich, germany ? 2012 infineon technologies ag all rights reserved. legal disclaimer the information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any ex amples or hints given herein, any typi cal values stated herein and/or any information regarding the application of the device, infi neon technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies components may be used in life-suppo rt devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
data sheet v1.4 2012-07 microcontrollers 32-bit tc1767 32-bit single-chip microcontroller
tc1767 data sheet 4 v1.4, 2012-07 trademarks tricore ? is a trademark of infineon technologies ag. tc1767 data sheet revision history: v1.4 2012-07 previous versions: v1.3 page subjects (major changes since last revision) page 6 salescode for copper-bonded device is added we listen to your comments is there any information in this document that you feel is wrong, unclear or missing? your feedback will help us to continuousl y improve the quality of this document. please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com
data sheet l-1 v1.4, 2012-07 tc1767 table of contents 1 summary of features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.1 about this document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.1.1 related documentations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.1.2 text conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.1.3 reserved, undefined, and unimplemented terminology . . . . . . . . . . 2-9 2.1.4 register access modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.1.5 abbreviations and acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.2 system architecture of the tc1767 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2.2.1 tc1767 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.2.2 system features of the tc1767 device . . . . . . . . . . . . . . . . . . . . . . 2-15 2.2.3 on chip cpu cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2.2.3.1 high-performance 32-bit cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2.2.3.2 high-performance 32-bit peripheral control processor . . . . . . . . . 2-17 2.3 on chip system units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 2.3.1 flexible interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 2.3.2 direct memory access controller . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.3.3 system timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 2.3.4 system control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 2.3.4.1 clock generation unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 2.3.4.2 features of the watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 2.3.4.3 reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 2.3.4.4 external interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 2.3.4.5 die temperature measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 2.3.5 general purpose i/o ports and peripheral i/o lines . . . . . . . . . . . . . 2-22 2.3.6 program memory unit (pmu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23 2.3.6.1 boot rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 2.3.6.2 overlay ram and data acquisition . . . . . . . . . . . . . . . . . . . . . . . . 2-24 2.3.6.3 emulation memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 2.3.6.4 tuning protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 2.3.6.5 program and data flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 2.3.7 data access overlay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27 2.3.8 tc1767 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28 2.4 on-chip peripheral units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29 2.4.1 asynchronous/synchronous se rial interfaces . . . . . . . . . . . . . . . . . . 2-29 2.4.2 high-speed synchronous seri al interfaces . . . . . . . . . . . . . . . . . . . . 2-32 2.4.3 micro second channel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34 2.4.4 multican controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36 2.4.5 micro link interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39 2.4.6 general purpose timer array (gpta) . . . . . . . . . . . . . . . . . . . . . . . . 2-41 table of contents
tc1767 table of contents data sheet l-2 v1.4, 2012-07 2.4.6.1 functionality of gpta0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42 2.4.7 analog-to-digital converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-45 2.4.7.1 adc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-45 2.4.7.2 fadc short description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-47 2.5 on-chip debug support (ocds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-49 2.5.1 on-chip debug support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-49 2.5.2 real time trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50 2.5.3 calibration support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50 2.5.4 tool interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51 2.5.5 self-test support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51 2.5.6 far support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51 3 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-52 3.1 tc1767 pin definition and functions . . . . . . . . . . . . . . . . . . . . . . . . . . 3-52 3.1.1 tc1767 pin configuration: pg-lqfp-176-5 . . . . . . . . . . . . . . . . . . . 3-53 3.1.2 reset behavior of the pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-75 4 identification registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-76 5 electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-78 5.1 general parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-78 5.1.1 parameter interpretati on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-78 5.1.2 pad driver and pad classes summary . . . . . . . . . . . . . . . . . . . . . . . 5-79 5.1.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-80 5.1.4 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-81 5.2 dc parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-84 5.2.1 input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-84 5.2.2 analog to digital converters (adc0/adc1) . . . . . . . . . . . . . . . . . . . 5-88 5.2.3 fast analog to digital converter (fadc) . . . . . . . . . . . . . . . . . . . . . . 5-93 5.2.4 oscillator pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-96 5.2.5 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-96 5.2.6 power supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-98 5.3 ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-100 5.3.1 testing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-100 5.3.2 output rise/fall times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-101 5.3.3 power sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-102 5.3.4 power, pad and reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-104 5.3.5 phase locked loop (pll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-106 5.3.6 jtag interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-109 5.3.7 dap interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-111 5.3.8 peripheral timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-113 5.3.8.1 micro link interface (mli) timing . . . . . . . . . . . . . . . . . . . . . . . . 5-113 5.3.8.2 micro second channel (msc) interfac e timing . . . . . . . . . . . . . 5-115 5.3.8.3 ssc master / slave mode timing . . . . . . . . . . . . . . . . . . . . . . . . 5-115
tc1767 table of contents data sheet l-3 v1.4, 2012-07 5.4 package and reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-118 5.4.1 package parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-118 5.4.2 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-119 5.4.3 flash memory parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-120 5.4.4 quality declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-121
tc1767 summary of features data sheet 4 v1.4, 2012-07 1 summary of features ? high-performance 32-bit super-scalar tricore v1.3.1 cpu with 4-stage pipeline ? superior real-time performance ? strong bit handling ? fully integrated dsp capabilities ? single precision floating point unit (fpu) ? 133 mhz operation at full temperature range ? 32-bit peripheral control processor with si ngle cycle instruction (pcp2) ? 8 kbyte parameter memory (pram) ? 16 kbyte code memory (cmem) ? 133 mhz operation at full temperature range ? multiple on-chip memories ? 72 kbyte data memory (ldram) ? 24 kbyte code scratchpad memory (spram) ? 2 mbyte program flash memory (pflash) ? 64 kbyte data flash memory (dfl ash, represents 16 kbyte eeprom) ? instruction cache: up to 8 kbyte (icache, configurable) ? data cache: up to 4 kbyt e (dcache, configurable) ? 8 kbyte overlay memory (ovram) ? 16 kbyte bootrom (brom) ? 8-channel dma controller ? sophisticated inte rrupt system with 2 255 hardware priority arbitration levels serviced by cpu or pcp2 ? high performing on-chip bus structure ? 64-bit local memory buses between cpu, flash and data memory ? 32-bit system peripheral bus (spb) for on-chip peripheral and functional units ? one bus bridge (lfi bridge) ? versatile on-chip peripheral units ? two asynchronous/synchronous serial channels (asc) with baud rate generator, parity, framing and overrun error detection ? two high-speed synchronous serial channels (ssc) with programmable data length and shift direction ? one serial micro second bus interface (msc) for serial port expansion to external power devices ? one high-speed micro link interface (mli) for serial inter-processor communication ? one multican module with 2 can nodes and 64 free assignable message objects for high efficiency data handling via fifo buffering and gateway data transfer ? one general purpose timer array modules (gpta) with additional local timer cell array (ltca2) providing a powerful set of digital signal filtering and timer functionality to realize autonomous and complex input/output management ? 32 analog input lines for adc
tc1767 summary of features data sheet 5 v1.4, 2012-07 ? 2 independent kernels (adc0, adc1) ? analog supply voltage range from 3.3 v to 5 v (single supply) ? performance for 12 bit resolution (@f adci =10 mhz) ? 4 different fadc input channels ? extreme fast conversion, 21 cycles of f fadc clock (262.5 ns @ f fadc = 80 mhz) ? 10-bit a/d conversion (higher resolution can be achieved by averaging of consecutive conversions in di gital data reduction filter) ? 88 digital general purpose i/o lines (gpio), 4 input lines ? digital i/o ports with 3.3 v capability ? on-chip debug support for ocds level 1 (cpu, pcp, dma, on chip bus) ? dedicated emulation device chip available (tc1767ed) ? multi-core debugging, real time tracing, and calibration ? four/five wire jtag (ieee 1149.1) or two wire dap (device access port) interface ? power management system ? clock generation unit with pll ? core supply voltage of 1.5 v ? i/o voltage of 3.3 v ? full automotive temperatur e range: -40 to +125c ? package variant: pg-lqfp-176-5
tc1767 summary of features data sheet 6 v1.4, 2012-07 ordering information the ordering code for infineon microcontro llers provides an exact reference to the required product. this ordering code identifies: ? the derivative itself, i.e. its function set, the temperature range, and the supply voltage ? the package and the type of delivery. for the available ordering codes for the tc1767 please refer to the ?product catalog microcontrollers? , which summarizes all available microcontroller variants. this document describes the de rivatives of the device.the table 1 enumerates these derivatives and summarizes the differences. table 1 tc1767 derivative synopsis derivative ambient temperature range cpu frequency wire bond material sak-tc1767-256f133hl t a = -40 o c to +125 o c 133 mhz gold sak-tc1767-256f80hl t a = -40 o c to +125 o c 80 mhz gold sak-tc1767-256f133hr t a = -40 o c to +125 o c 133 mhz copper
tc1767 introduction data sheet 7 v1.4, 2012-07 2 introduction this data sheet describes the infineon tc176 7, a 32-bit microcontroller dsp, based on the infineon tricore architecture. 2.1 about this document this document is designed to be read pr imarily by design engineers and software engineers who need a detailed description of the interactions of the tc1767 functional units, registers, instru ctions, and exceptions. this tc1767 data sheet describes the feat ures of the tc1767 with respect to the tricore architecture. where the tc1767 dire ctly implements tricore architectural functions, this manual simply re fers to those functions as features of the tc1767. in all cases where this manual describes a tc 1767 feature without re ferring to the tricore architecture, this means that the tc1767 is a direct implement ation of the tricore architecture. where the tc1767 implements a subset of tricore architec tural features, this manual describes the tc1767 implementation, and then describes how it differs from the tricore architecture. such differences between the tc1767 and the tricore architecture are documented in the section covering each such subject. 2.1.1 related documentations a complete description of the tricore archit ecture is found in the document entitled ?tricore architecture manual?. the architec ture of the tc1767 is described separately this way because of the configurable nature of the tricore specification: different versions of the architecture may contain a different mi x of systems components. the tricore architecture, however, remains consta nt across all derivative designs in order to preserve compatibility. this data sheets together with the ?tr icore architecture manual? are required to understand the complete tc1767 mi cro controller functionality. 2.1.2 text conventions this document uses the following text conventions for named components of the tc1767: ? functional units of the tc1767 are given in plain upper case. for example: ?the ssc supports full-duplex and half- duplex synchronous communication?. ? pins using negative logic are indicated by an overline. for example: ?the external reset pin, esr0 , has a dual function.?. ? bit fields and bits in register s are in general referenced as ?module_register name.bit field? or ?module_register name.bit?. for example: ?the current cpu priority number bit field cp u_icr.ccpn is cleared?. most of the
tc1767 introduction data sheet 8 v1.4, 2012-07 register names contain a module name prefix , separated by an underscore character ?_? from the actual register name (for ex ample, ?asc0_con?, where ?asc0? is the module name prefix, and ?con? is the kernel register name). in chapters describing the kernels of the peripheral modules, the registers are mainly referenced with their kernel register names. the peripheral modu le implementation sections mainly refer to the actual register names with module prefixes. ? variables used to describe sets of proc essing units or registers appear in mixed upper and lower cases. for example, regi ster name ?msgcfgn? refers to multiple ?msgcfg? registers with variable n. the bounds of the variables are always given where the register expression is first used (for example, ?n = 0-31?), and are repeated as needed in the rest of the text. ? the default radix is decimal. hexadecima l constants are suffix ed with a subscript letter ?h?, as in 100 h . binary constants are suffixed with a subscript letter ?b?, as in: 111 b . ? when the extent of register fields, groups register bits, or groups of pins are collectively named in the body of th e document, they are represented as ?name[a:b]?, which defines a range for the named group from b to a. individual bits, signals, or pins are given as ?name[c]? wh ere the range of the variable c is given in the text. for example: cfg[2:0] and srpn[0]. ? units are abbreviated as follows: ? mhz = megahertz ? s = microseconds ? kbaud, kbit = 1000 characters/bits per second ? mbaud, mbit = 1,000,000 characters/bits per second ? kbyte, kb = 1024 bytes of memory ? mbyte, mb = 1048576 bytes of memory in general, the k prefix scales a unit by 1000 whereas the k prefix scales a unit by 1024. hence, the kbyte unit scales the ex pression preceding it by 1024. the kbaud unit scales the expression preceding it by 1000. the m prefix scales by 1,000,000 or 1048576, and scales by .000001. for example, 1 kbyte is 1024 bytes, 1 mbyte is 1024 1024 bytes, 1 kbaud/kbit are 1000 characters/bits per second, 1 mbaud/mbit are 1000000 characters/bits per second, and 1 mhz is 1,000,000 hz. ? data format quantities are defined as follows: ? byte = 8-bit quantity ? half-word = 16-bit quantity ? word = 32-bit quantity ? double-word = 64-bit quantity
tc1767 introduction data sheet 9 v1.4, 2012-07 2.1.3 reserved, undefined, and unimplemented terminology in tables where register bit fields are defined, the following conventions are used to indicate undefined and unimplemented function. furthermore, types of bits and bit fields are defined using the abbreviations as shown in table 2 . 2.1.4 register access modes read and write access to registers and memo ry locations are sometimes restricted. in memory and register access tables, the terms as defined in table 3 are used. table 2 bit function terminology function of bits description unimplemented, reserved register bit fields named 0 indicate unimplemented functions with the following behavior. ? reading these bit fields returns 0. ? these bit fields should be written with 0 if the bit field is defined as r or rh. ? these bit fields have to be written with 0 if the bit field is defined as rw. these bit fields are reserved. the detailed description of these bit fields can be found in the register descriptions. rw the bit or bit field can be read and written. rwh as rw, but bit or bit field can be also set or reset by hardware. r the bit or bit field can only be read (read-only). w the bit or bit field can only be written (write-only). a read to this register will always give a default value back. rh this bit or bit field can be modified by hardware (read-hardware, typical example: status flags). a r ead of this bit or bit field give the actual status of this bit or bit field back. writing to this bit or bit field has no effect to the setting of this bit or bit field. s bits with this attribute are ?sticky? in one direction. if their reset value is once overwritten by software, they can be switched again into their reset state only by a reset operation. software cannot switch this type of bit in to its reset state by writing the register. this attribute can be combined to ?rws? or ?rwhs?. f bits with this attribute are readable only when they are accessed by an instruction fetch. normal data read operations will return other values.
tc1767 introduction data sheet 10 v1.4, 2012-07 2.1.5 abbreviations and acronyms the following acronyms and terms are used in this document: table 3 access terms symbol description u access mode: access permitted in user mode 0 or 1. reset value: value or bit is not changed by a reset operation. sv access permitted in supervisor mode. r read-only register. 32 only 32-bit word accesses are permi tted to this register/address range. e endinit-protected register/address. pw password-protected register/address. nc no change, indicated register is not changed. be indicates that an access to this address range generates a bus error. nbe indicates that no bus error is generated when accessing this address range, even though it is either an access to an undefined address or the access does not follow the given rules. ne indicates that no error is generat ed when accessing this address or address range, even though the acce ss is to an undefined address or address range. true for cpu accesses (mtcr/mfcr) to undefined addresses in the csfr range. adc analog-to-digital converter agpr address general purpose register alu arithmetic and logic unit asc asynchronous/synchronous serial controller bcu bus control unit brom boot rom & test rom can controller area network cmem pcp code memory cisc complex instruction set computing cps cpu slave interface cpu central processing unit
tc1767 introduction data sheet 11 v1.4, 2012-07 csa context save area csfr core special function register dap device access port das device access server dcache data cache dflash data flash memory dgpr data general purpose register dma direct memory access dmi data memory interface eru external request unit emi electro-magnetic interference fadc fast analog-to-digital converter fam flash array module fcs flash command state machine fim flash interface and control module fpi flexible peripheral interconnect (bus) fpu floating point unit gpio general purpose input/output gpr general purpose register gpta general purpose timer array icache instruction cache i/o input / output jtag joint test action group = ieee1149.1 lbcu local memory bus control unit ldram local data ram lfi local memory-to- fpi bus interface lmb local memory bus ltc local timer cell mli micro link interface mmu memory management unit msb most significant bit msc micro second channel
tc1767 introduction data sheet 12 v1.4, 2012-07 nc non connect nmi non-maskable interrupt ocds on-chip debug support ovram overlay memory pcp peripheral control processor pmu program memory unit pll phase locked loop pflash program flash memory pmi program memory interface pmu program memory unit pram pcp parameter ram ram random access memory risc reduced instruction set computing sbcu system peripheral bus control unit scu system control unit sfr special function register spb system peripheral bus spram scratch-pad ram sram static data memory srn service request node ssc synchronous serial controller stm system timer wdt watchdog timer
tc1767 introduction data sheet 13 v1.4, 2012-07 2.2 system architecture of the tc1767 the tc1767 combines three powerful technologies within one silicon die, achieving new levels of power, speed, and economy for embedded applications: ? reduced instruction set computing (risc) processor architecture ? digital signal processing (dsp) operations and addressing modes ? on-chip memories and peripherals dsp operations and addressing modes prov ide the computational power necessary to efficiently analyze complex real-world signals. the risc load/store architecture provides high computational bandwidth with low system cost. on-chip memory and peripherals are designed to support even th e most demanding high-bandwidth real-time embedded control-systems tasks. additional high-level featur es of the tc1767 include: ? program memory unit ? instruct ion memory and instruction cache ? serial communication interfaces ? flexible synchronous and asynchronous modes ? peripheral control processor ? standalon e data operations and interrupt servicing ? dma controller ? dma operations and interrupt servicing ? general-purpose timers ? high-performance on-chip buses ? on-chip debugging and emulation facilities ? flexible interconnections to external components ? flexible power-management tc1767 clock frequencies: ? maximum cpu clock frequency: 133 mhz 1) ? maximum pcp clock frequency: 133 mhz 2) ? maximum spb frequency: 80 mhz 3) the tc1767 is a high-performance microcontroller with tricore cpu, program and data memories, buses, bus arbitration, an interrupt controller, a peripheral control processor, a dma controller and several on-chip peripherals. the tc1767 is designed to meet the needs of the most demanding embedded cont rol systems applications where the competing issues of price/performance, re al-time responsiveness, computational power, data bandwidth, and power consumption are key design elements. the tc1767 offers several versatile on-chip per ipheral units such as serial controllers, timer units, and analog-to-digital converte rs. within the tc1767, all these peripheral units are connected to the tricore cpu/system via the flexible peripheral interconnect (fpi) bus and the local memory bus (lmb). several i/o lines on the tc1767 ports are reserved for these peripheral units to communicate with the external world. 1) for cpu frequencies > 80 mhz, 2:1 mode has to be enabled. cpu 2:1 mode means: f spb = 0.5 * f cpu 2) for pcp frequencies > 80 mhz, 2:1 mode has to be enabled. pcp 2:1 mode means: f spb = 0.5 * f pcp 3) cpu 1:1 mode means: f spb = f cpu . pcp 1:1 mode means: f spb = f pcp
tc1767 introduction data sheet 14 v1.4, 2012-07 2.2.1 tc1767 block diagram figure 1 shows the block diagram of the tc1767. figure 1 tc1767 block diagram fadc ( 3.3v) 4 diff ch . interrupt system lbcu lfi bridge ocds debug interface/ jtag tricore cpu 1 6 kb spram 8 kb i cache (configurable ) 68 kb ldram 4 kb dcache (configurable) cps local memory bus (lmb) 2 mb pflash 64 kb dflash 8 kb ovram 1 6 kb brom pmu fp u dma (8 channels) smif mli 0 m/ s 1,5v, 3.3v ext. supply fpi-bus interface 8 kb pram pcp2 core 16 kb cmem interrupts f pl l system peripheral bus (spb) ports scu blockdiagram tc 1767 lqfp -176 multi can (2 nodes, 64 buffer) stm ext. request unit pll sbcu msc0 (lvds) ssc1 ssc0 asc1 asc0 5v ext. adc supply 28 adc0 16 channels adc1 16 channels memcheck abbreviations: icache: instruction cache dcache data cache spram : scra t ch -pa d ram ldram: local data ram ovram: overlay ram brom: boot rom pflash : program flash dflash: data flash pram: parameter ram in pcp cm em: cod e ram in pcp m (3.3v max) (5v max) 4 4 pmi dmi ltca2 gtpa0
tc1767 introduction data sheet 15 v1.4, 2012-07 2.2.2 system features of the tc1767 device the tc1767 has the following features: packages ? pg-lqfp-176-5 package, 0.5 mm pitch clock frequencies ? maximum cpu clock frequency: 133 mhz 1) ? maximum pcp clock frequency: 133 mhz 2) ? maximum spb clock frequency: 80 mhz 3) 1) for cpu frequencies > 80 mhz, 2:1 mode has to be enabled. cpu 2:1 mode means: f spb = 0.5 * f cpu 2) for pcp frequencies > 80 mhz, 2:1 mode has to be enabled. pcp 2:1 mode means: f spb = 0.5 * f pcp 3) cpu 1:1 mode means: f spb = f cpu . pcp 1:1 mode means: f spb = f pcp
tc1767 introduction data sheet 16 v1.4, 2012-07 2.2.3 on chip cpu cores the tc1767 includes a high performance cpu and a peripheral control processor. . 2.2.3.1 high-performance 32-bit cpu this chapter gives an overview about the tricore 1 architecture. tricore (tc1.3.1) arch itectural highlights ? unified risc mcu/dsp ? 32-bit architecture with 4 gbytes unifie d data, program, and input/output address space ? fast automatic c ontext-switching ? multiply-accumulate unit ? floating point unit ? saturating inte ger arithmetic ? high-performance on-chip peripheral bus (fpi bus) ? register based design with mult iple variable register banks ? bit handling ? packed data operations ? zero overhead loop ? precise exceptions ? flexible power management high-efficiency tricore instruction set ? 16/32-bit instructions for reduced code size ? data types include: boolean, array of bi ts, character, signed and unsigned integer, integer with saturation, signed fraction, double-word integers, and ieee-754 single- precision floating point ? data formats include: bit, 8-bit byte, 16-b it half-word, 32-bit word, and 64-bit double- word data formats ? powerful instruction set ? flexible and efficient addressing mode for high code density integrated cpu rela ted on-chip memories ? instruction memory: 24 kb total. after reset, configured into: 1) ? 24 kbyte scratch-pad ram (spram) ? 0 kbyte instruction cache (icache) ? data memory: 72 kb total. after reset, configured into: 1) 1) software configurable. available options are described in the cpu chapter.
tc1767 introduction data sheet 17 v1.4, 2012-07 ? 72 kbyte local data ram (ldram) ? 0 kbyte data cache (dache) ? on-chip srams with parity error detection 2.2.3.2 high-performance 32-bit peripheral control processor the pcp is a flexible peripheral control processor optimized for interrupt handling and thus unloading the cpu. features ? data move between any two memory or i/o locations ? data move with predefined limit supported ? read-modify-write capabilities ? full computation capabilities including basic mul/div ? read/move data and accumulate it to previously read data ? read two data values and perform arithm etic or logical operation and store result ? bit-handling capabilities (testing, setting, clearing) ? flow control instructions (conditi onal/unconditional jumps, breakpoint) ? dedicated interrupt system ? pcp srams with parity error detection ? pcp/fpi clock mode 1:1 and 2:1 available integrated pcp related on-chip memories ? 16 kbyte code memory (cmem) ? 8 kbyte parameter memory (pram) ? 2.3 on chip system units the tc1767 micro controller offers several versatile on-chip system peripheral units such as dma controller, embedded flash module, interrupt system and ports. 2.3.1 flexible interrupt system the tc1767 includes a programmable interr upt system with the following features: features ? fast interrupt response ? hardware arbitration ? independent interrupt systems for cpu and pcp ? programmable service request nodes (srns) ? each srn can be mapped to the cpu or pcpinterrupt system
tc1767 introduction data sheet 18 v1.4, 2012-07 ? flexible interrupt-prioritizing scheme with 255 interrupt priority levels per srn to choose from 2.3.2 direct memory access controller the tc1767 includes a fast and flexible dma controller with independant dma channels ( dma move engine). features ? independent dma channels ? up to 16 selectable request inputs per dma channel ? 2-level programmable priority of dma channels within the dma sub-block ? software and hardware dma request ? hardware requests by selected on-ch ip peripherals and external inputs ? 3-level programmable priority of the dma sub-block at the on chip bus interfaces ? buffer capability for move actions on the buses (at least 1 move per bus is buffered) ? individually programmable operation modes for each dma channel ? single mode: stops and disables dma c hannel after a predefined number of dma transfers ? continuous mode: dma channel remains enabled after a predefined number of dma transfers; dma transaction can be repeated ? programmable address modification ? two shadow register modes (with / w/o automatic re-set and direct write access). ? full 32-bit addressing capability of each dma channel ? 4 gbyte address range ? data block move supports > 32 kbyte moves per dma transaction ? circular buffer addressing mode with flexible circular buffer sizes ? programmable data width of dma transfer/ transaction: 8-bit, 16-bit, or 32-bit ? register set for each dma channel ? source and destination address register ? channel control and status register ? transfer count register ? flexible interrupt generation (the service request node logic for the mli channel is also implemented in the dma module) ? dma module is working on spb frequency, lmb interface on lmb frequency. ? dependant on the target/destination addre ss, read/write requests from the move engine are directed to the spb, lmb, mli or to the the cerberus.
tc1767 introduction data sheet 19 v1.4, 2012-07 2.3.3 system timer the tc1767?s stm is designed for global system ti ming applications requiring both high precision and long range. features ? free-running 56-bit counter ? all 56 bits can be read synchronously ? different 32-bit portions of the 56- bit counter can be read synchronously ? flexible interrupt generation based on compare match with partial stm content ? driven by maximum 80 mhz (= f sys , default after reset = f sys /2) ? counting starts automatically after a reset operation ? stm registers are reset by an application re set if bit arstdis.stmdis is cleared. if bit arstdis.stmdis is set, the stm is not reset. ? stm can be halted in debug/suspend mode special stm register semantics provide syn chronous views of the entire 56-bit counter, or 32-bit subsets at different levels of resolution. the maximum clock period is 2 56 f stm . at f stm = 80 mhz, for example, the stm counts 28.56 years before overflowing. thus, it is capable of continuously timing the entire expected product life time of a system without overflowing. in case of a power-on reset, a watchdog reset, or a software reset, the stm is reset. after one of these reset conditions, the stm is ena bled and immediately starts counting up. it is not possible to affect the content of the timer during normal operation of the tc1767. the timer registers can only be read but not written to. the stm can be optionally disabled for power-saving purposes, or suspended for debugging purposes via its clock control register. in suspend mode of the tc1767 (initiated by writing an appropriate value to stm_clc register), the stm clock is stopped but all registers are still readable. due to the 56-bit width of the stm, it is not possible to r ead its entire content with one instruction. it needs to be read with two lo ad instructions. since the timer would continue to count between the two load operations, ther e is a chance that the two values read are not consistent (due to possible overflow from the low part of the timer to the high part between the two read operations). to enabl e a synchronous and consistent reading of the stm content, a capture re gister (stm_cap) is implemented. it latches the content of the high part of the stm each time when one of the registers stm_tim0 to stm_tim5 is read. thus, stm_cap holds the upper value of the timer at exactly the same time when the lower part is read. the second read operation would t hen read the content of the stm_cap to get the complete timer value. the content of the 56 -bit system timer can be compar ed against the content of two compare values stored in the stm_cmp0 a nd stm_cmp1 registers. interrupts can be
tc1767 introduction data sheet 20 v1.4, 2012-07 generated on a compare match of the stm with the stm_cmp0 or stm_cmp1 registers. figure 2 provides an overview on the stm m odule. it shows the options for reading parts of stm content. figure 2 general block diagram of the stm module registers stm module 00 h stm_cap stm_tim6 stm_tim5 00 h 56-bit system timer address decoder clock control mcb06185_mod compare register 0 interrupt control compare register1 porst stm_tim4 stm_tim3 stm_tim2 stm_tim1 stm_tim0 stm_cmp1 stm_cmp0 enable / disable f stm stm irq0 31 23 15 7 0 31 23 15 7 0 55 47 39 31 23 15 7 0 stm irq1 to dma etc.
tc1767 introduction data sheet 21 v1.4, 2012-07 2.3.4 system control unit the following scu introduction gives an ov erview about the tc 1767 system control unit (scu). 2.3.4.1 clock generation unit the clock generation unit (cgu) allows a very flexible clock generation for the tc1767. during user program execution the frequency can be programmed for an optimal ratio between performance and power consumption. 2.3.4.2 features of the watchdog timer the main features of the wdt are summarized here. ? 16-bit watchdog counter ? selectable input frequency: f fpi /256 or f fpi /16384 ? 16-bit user-definable reload value for normal watchdog operation, fixed reload value for time-out and prewarning modes ? incorporation of the e ndinit bit and monitori ng of its modifications ? sophisticated password acce ss mechanism with fixed and user-definable password fields ? access error detection: inva lid password (during first access) or invalid guard bits (during second access) trigger the watchdog reset generation ? overflow error detection: an overflow of the counter triggers the watchdog reset generation ? watchdog function can be disabled; acce ss protection and endinit monitor function remain enabled ? double reset detection: if a watchdog i nduced reset occurs t wice, a severe system malfunction is assumed and the tc1767 is held in reset until a system / class 0 reset occurs. 2.3.4.3 reset operation the following reset request triggers are available: ? 1 external power-on hardware reset request trigger; porst , (cold reset) ? 2 external system request reset triggers; esr0 and esr1 (warm reset) ? watchdog timer (wdt) reset request trigger, (warm reset) ? software reset (sw), (warm reset) ? debug (ocds) reset request trigger, (warm reset) ? jtag reset (special reset) ? resets via the jtag interface note: the jtag and ocds resets ar e described in the ocds chapter. there are two basic types of reset request triggers:
tc1767 introduction data sheet 22 v1.4, 2012-07 ? trigger sources that do not depend on a clock, such as the porst . this trigger force the device into an asynchronous reset assertion independently of any clock. the activation of an asynchronous reset is a synchronous to the system clock, whereas its de-assertion is synchronized. ? trigger sources that need a clock in order to be asserted, such as the input signals esr0 , and esr1 , the wdt trigger, the parity trigger, or the sw trigger. 2.3.4.4 external interface the scu provides inte rface pads for system purpose. various functions are covered by these pins. due to the different tasks some of the pads can not be shared with other functions but most of them can be shared with other functions. the following functions are covered by the scu controlled pads: ? reset request triggers ? reset indication ? trap request triggers ? interrupt request triggers ? non scu module triggers the first three points are covered by the esr pads and the last two points by the eru pads. 2.3.4.5 die temperature measurement the die temperature sensor (dts) generates a measurement result that indicates directly the current temperatur e. the result of the measurement can be read via an dts register. 2.3.5 general purpose i/o ports and peripheral i/o lines the tc1767 includes a flexible ports structure with the fo llowing features: features ? digital general-purpose in put/output (gpio) port lines ? input/output functionality individual ly programmable for each port line ? programmable input characteristi cs (pull-up, pull-down, no pull device) ? programmable output driver strength for emi minimization (weak, medium, strong) ? programmable output characteri stics (push-pull, open drain) ? programmable alternate output functions ? output lines of each port can be updat ed port-wise or set/reset/toggled bit-wise
tc1767 introduction data sheet 23 v1.4, 2012-07 2.3.6 program memory unit (pmu) the devices of the audof family contain at least one program memory unit. this is named ?pmu0?. some devices contain additional pmus which are named ?pmu1?, ? in the tc1767, the pmu0 contains the following submodules: ? the flash command and fetch control interface for program flash and data flash. ? the overlay ram interface with onlin e data acquisition (olda) support. ? the boot rom interface. ? the emulation memory interface. ? the local memory bus lmb slave interface. following memories are controlled by and belong to the pmu0: ? 2 mbyte of program fl ash memory (pflash) ? 64 kbyte of data flash memory (dflash, represents 16 kbyte eeprom) ? 16 kbyte of boot rom (brom) ? 8 kbyte overlay ram (ovram) the following figure shows the block diagram of the pmu0: figure 3 pmu0 basic block diagram pmu0 pmu0_basicblockdiag _generic pmu control overlay ram interface emulation memory (ed chip only ) flash interface module dflash pflash 64 rom control brom 64 emulation memory interface ovram 64 to/from local memory bus lmb interface slave 64 64 64 64
tc1767 introduction data sheet 24 v1.4, 2012-07 2.3.6.1 boot rom the internal 16 kbyte boot rom (brom) is divided into two parts, used for: ? firmware (boot rom), and ? factory test routines (test rom). the different sections of the firmware in boot rom provide startup and boot operations after reset. the testrom is reserved for special routines, which are used for testing, stressing and qualification of the component. 2.3.6.2 overlay ram and data acquisition the overlay memory ovram is provided in the pmu especially for redirection of data accesses to program memory to the ovram by using the data overlay function. the data overlay functionality itself is controlled in the dmi module. for online data acquisition (olda) of applic ation or calibration data a virtual 32 kb memory range is provided which can be a ccessed without error reporting. accesses to this olda range can also be redirected to an overlay memory. 2.3.6.3 emulation memory interface in tc1767 emulation device, an emulation memory (emem) is provided, which can fully be used for calibration via program memory or olda overlay. the emulation memory interface shown in figure 3 is a 64-bit wide memory interface that controls the cpu- accesses to the emulation memory in the tc1767 emulation device. in the tc1767 production device, the emem interface is always disabled. 2.3.6.4 tuning protection tuning protection is required by the user to absolutely protect control data (e.g. for engine control), serial number and user software, stored in the flash, from being manipulated, and to safely detect changed or disturbed data. for the internal flash, these protection requirements are exce llently fulfilled in the tc1767 with ? flash read and write protection with user-specific protection levels, and with ? dedicated hw and firmware, supporting the internal flash read protection, and with ? the alternate boot mode. special tuning protection support is provid ed for external flash, which must also be protected. 2.3.6.5 program and data flash the embedded flash module of pmu0 includes 2 mbyte of flash memory for code or constant data (called program flash) and additionally 64 kbyte of flash memory used for emulation of eeprom data (called data flash). the program flash is realized as
tc1767 introduction data sheet 25 v1.4, 2012-07 one independent flash bank, whereas the da ta flash is built of two flash banks, allowing the following combinations of concurrent flash operations: ? read code or data from program flash, while one bank of data flash is busy with a program or erase operation. ? read data from one bank of data flash, wh ile the other bank of data flash is busy with a program or erase operation. ? program one bank of data flash while er asing the other bank of data flash, read from program flash. both, the program flash and the data flash, provide error correction of single-bit errors within a 64-bit read double-word, resulting in an extremely low failure rate. read accesses to program flash are executed in 256- bit width, to data flash in 64-bit width (both plus ecc). single-cycle burst transf ers of up to 4 double-words and sequential prefetching with control of prefetch hit are supported for program flash. the minimum programming width is the page, including 256 bytes in program flash and 128 bytes in data flash. concurrent programming and erasing in data flash is performed using an automatic erase suspend and resume function. a basic block diagram of the flash modu le is shown in the following figure. figure 4 basic block diagram of flash module all flash operations are cont rolled simply by transferring command sequences to the flash which are based on jedec standard. this user interface of the embedded flash is very comfortable, because all operat ions are controlled with high level commands, such as ?erase sector?. state transitions, such as termination of command execution, or errors are reported to the user by maskable interrupts. command sequences are page write buffers 256 byte and 128 byte pf-read buffer 256 + 32 bit and df-read buffer 64 + 8 bit voltage control flash array module fam bank 0 program flash ecc block 8 ecc code wr_data rd_data flash interface&control module fim 64 64 64 64 read bus write bus flash command state machine fcs addr bus control fsi address control flash_basicblockdiagram_generic.vsd pmu bank 1 data flash bank 0 bank 1 flash fsi & array redundancy control sfrs fsram microcode 8
tc1767 introduction data sheet 26 v1.4, 2012-07 normally written to flash by the cpu, but may also be issued by the dma controller (or ocds). the flash also features an advanced read/write protection architecture, including a read protection for the whole flash array (opti onally without data flash) and separate write protection for all sectors (only program flash) . write protected sectors can be made re- programmable (enabled with passwords), or t hey can be locked for ever (rom function). each sector can be assigned to up to thr ee different users for write protection. the different users are organized hierarchically. program flash features and functions ? 2 mbyte on-chip program flash in pmu0. ? any use for instruction code or constant data. ? 256 bit read interface (burst transfer operation). ? dynamic correction of single-bit errors during read access. ? transfer rate in burst mode: one 64-bit double-word per clock cycle. ? sector architecture: ? eight 16 kbyte, one 128 kbyte and seven 256 kbyte sectors. ? each sector separately erasable. ? each sector lockable for protection agai nst erase and program (write protection). ? one additional configuration sector (not accessible to the user). ? optional read protection for whole flash, with sophisticated read access supervision. combined with whole flash write protection ? thus supporting protection against trojan horse programs. ? sector specific write protection with suppo rt of re-programmability or locked forever. ? comfortable password checking for tempor ary disable of write or read protection. ? user controlled configuration blocks (ucb) in configurati on sector for keywords and for sector-specific lock bits (one block for every user; up to three users). ? pad supply voltage (v ddp ) also used for progra m and erase (no vpp pin). ? efficient 256 byte page program operation. ? all flash operations controlled by cpu per command sequences (unlock sequences) for protection against unintended operation. ? end-of-busy as well as error reporting with interrupt and bus error trap. ? write state machine for automatic progr am and erase, including verification of operation quality. ? support of margin check. ? delivery in erased state (read all zeros). ? global and sector status information. ? overlay support with sram for calibration applications. ? configurable wait state selectio n for different cpu frequencies. ? endurance = 1000; minimum 1000 program/erase cycles per physical sector; reduced endurance of 100 per 16 kb sector. ? operating lifetime (incl. retention): 20 years with endurance=1000.
tc1767 introduction data sheet 27 v1.4, 2012-07 ? for further operating conditions see data sheet section ?flash memory parameters?. data flash features and functions ? 64 kbyte on-chip flash, configured in two independent flash banks of equal size. ? 64 bit read interface. ? erase/program one bank while data read access from the other bank. ? programming one bank while erasin g the other bank using an automatic suspend/resume function. ? dynamic correction of single-bit errors during read access. ? sector architecture: ? two sectors of equal size. ? each sector separately erasable. ? 128 byte pages to be written in one step. ? operational control per command sequences (unlock sequences, same as those of program flash) for protecti on against unintended operation. ? end-of-busy as well as error reporting with interrupt and bus error trap. ? write state machine for automatic program and erase. ? margin check for detection of problematic flash bits. ? endurance = 30000 (can be device dependent); i.e. 30000 program/erase cycles per sector are allowed, with a retention of min. 5 years. ? dedicated dflash status information. ? other characteristics: same as program flash. 2.3.7 data access overlay the data overlay functionality provides the capability to redirect data accesses by the tricore to program memory (segments 8 h and a h ) called ?target memory? to a different memory called ?overlay memory?. depending on the device the following overlay memories can be available: ? overlay sram in the pmu. ? emulation memory 1) . ? external memory 2) . this functionality makes it possible, for exam ple, to modify the application?s test and calibration parameters (which are typically stored in the program memory) during run time of a program. as the address translation is implemented in the dmi, it affects only data accesses (reads and writes) of the tricor e. instruction fetches by the tricore or accesses by any other master (including the debug interface) are not redirected. 1) only available in emulation device ?ed?. 2) only available in emulation device with ebu.
tc1767 introduction data sheet 28 v1.4, 2012-07 summary of features and functions ? 16 overlay ranges (?blocks?) configurable. ? support of 8 kbyte embedded overlay sram (ovram) in pmu. ? support of up to 256 kbyte over lay/calibration memory (emem) 1) . ? support of up to 2 mb overlay memory in external memory (ebu space) 2) . ? support of online data acquisition into range of up to 32 kb and of its overlay. ? support of different overlay memory sele ctions for every enabled overlay block. ? sizes of overlay blocks selectable depending on the overlay memory: ? ovram: from 16 byte to 2 kbyte. ?emem 1) and external memory 2) : 1 kbyte to 128 kbyte. ? all configured overlay ranges can be en abled with only one register write access. ? programmable flush (invalidate) control for data cache in dmi. 2.3.8 tc1767 development support overview about the tc176 7 development environment: complete development support a variety of software and hardware development tools for the 32-bit microcontroller tc1767 are available from experienced inte rnational tool suppliers. the development environment for the infineon 32-bit microc ontroller includes the following tools: ? embedded development environment for tricore products ? the tc1767 on-chip debug support (ocds) provides a jtag port for communication between extern al hardware and the system ? the system timer (stm) with high-precision, long-range timing capabilities ? the tc1767 includes a power management system, a watchdog timer as well as reset logic
tc1767 introduction data sheet 29 v1.4, 2012-07 2.4 on-chip peripheral units the tc1767 micro controller offers several versatile on-chip peripheral units such as serial controllers, timer units, and analog-to -digital converters. several i/o lines on the tc1767 ports are reserved for these peripher al units to communicate with the external world. on-chip peripheral units ? two asynchronous/synchronous serial c hannels (asc) with baud-rate generator, parity, framing and overrun error detection ? two synchronous serial channels (ssc ) with programmable data length and shift direction ? one micro second bus interface (msc) for serial communication ? one can module (multican) for high-effic iency data handling via fifo buffering and gateway data transfer ? one micro link serial bus interfaces (ml i) for serial multip rocessor communication ? one general purpose timer array (gpta) with a powerful set of digital signal filtering and timer functionality to accomplish autonomous and complex input/output management ? two analog-to-digital converter units (a dc0, adc1) with 8-bit, 10-bit, or 12-bit resolution. ? one fast analog-to-digital converter unit (fadc) 2.4.1 asynchronous/synchronous serial interfaces the tc1767 includes two asynchronous/synchronous serial interfaces, asc0 and asc1. both asc modules have the same functionality.and asc1both asc modules have the same functionality. figure 5 shows a global view of the asynchronous/synchronous serial interface (asc).
tc1767 introduction data sheet 30 v1.4, 2012-07 figure 5 general block diagram of the asc interface the asc provides serial communication between the tc1767 and other microcontrollers, microprocessors, or external peripherals. the asc supports full-duplex asynchronous communication and half-duplex synchronous communication. in synchronous mode, data is transmitted or received synchronous to a shift clock that is generated by the asc internally. in asynchronous mode, 8-bit or 9-bit data transfer, parity g eneration, and the number of stop bits can be selected. parity, framing, and overrun erro r detection are provided to increase the reliability of data transfers. transmission an d reception of data is double-buffered. for multiprocessor communication, a mechanism is included to distinguish address bytes from data bytes. testing is supported by a loop-back option. a 13-bit baud rate generator provides the asc with a separate serial clock signal, which can be accurately adjusted by a prescaler implemented as fractional divider. mcb05762_mod clock control address decoder interrupt control f asc asc module (kernel) port control rxd txd rxd txd to dma eir tbir tir rir
tc1767 introduction data sheet 31 v1.4, 2012-07 features ? full-duplex asynchronous operating modes ? 8-bit or 9-bit data frames, lsb first ? parity-bit generation/checking ? one or two stop bits ? baud rate from 5.0 mbit/s to 1.19 bit/s (@ 80 mhz module clock) ? multiprocessor mode for automatic address/data byte detection ? loop-back capability ? half-duplex 8-bit synchronous operating mode ? baud rate from 10.0 mbit/s to 813.8 bit/s (@ 80 mhz module clock) ? double-buffered transmitter/receiver ? interrupt generation ? on a transmit buffer empty condition ? on a transmit last bit of a frame condition ? on a receive buffer full condition ? on an error condition (fra me, parity, overrun error) ? implementation features ? connections to dma controller ? connections of receiver input to gpta (ltc) for baud rate detection and lin break signal measuring
tc1767 introduction data sheet 32 v1.4, 2012-07 2.4.2 high-speed synchronous serial interfaces the tc1767 includes two high-speed synchronous serial interfaces, ssc0 and ssc1. both ssc modules have the same functionality. figure 6 shows a global view of the synchronous serial interface (ssc). figure 6 general block diag ram of the ssc interface the ssc supports full-duplex and half-duplex serial synchronous communication up to 40 mbit/s (@ 80 mhz module clock, master mode). the serial clock signal can be generated by the ssc itself (master mode) or can be received from an external master (slave mode). data width, shift direction, clock polarity and phase are programmable. this allows communication with spi-compa tible devices. transmission and reception of data are double-buffered. a shift clock gener ator provides the ssc with a separate serial clock signal. one slave select input is available for slave mode operation. eight programmable slave select outputs (chi p selects) are supported in master mode. mcb06058_mod clock control address decoder interrupt control f ssc ssc module (kernel) mrstb mtsr master rir tir eir slsi[7:1] slsi[7:1] slso[7:0] slso[7:0] mrst mtsr sclk mrsta mtsrb mrst mtsra sclkb sclk sclka slave slave master slave master port control f clc enable m/s select dma requests slsoando[7:0] slsoando[7:0] slsoandi[7:0]
tc1767 introduction data sheet 33 v1.4, 2012-07 features ? master and slave mode operation ? full-duplex or half-duplex operation ? automatic pad control possible ? flexible data format ? programmable number of data bits: 2 to 16 bits ? programmable shift directio n: lsb or msb shift first ? programmable clock polarity: idle low or idle high state for the shift clock ? programmable clock/data phase: data shift with leading or trailing edge of the shift clock ? baud rate generation ? master mode: 40.0 mbit/s to 610.36 bit/s (@ 80 mhz module clock) ? slave mode: 20 mbit/s to 610.3 6 bit/s (@ 80 mhz module clock) ? interrupt generation ? on a transmitter empty condition ? on a receiver full condition ? on an error condition (receive, phase, baud rate, transmit error) ? flexible ssc pin configuration ? seven slave select inputs slsi[7:1] in slave mode ? eight programmable slave select outputs slso in master mode ? automatic slso generation with programmable timing ? programmable active level and enable control
tc1767 introduction data sheet 34 v1.4, 2012-07 2.4.3 micro second channel interface the micro second channel (msc) interface provides serial communication links typically used to connect power switches or other peripheral devices. the serial communication link includes a fast synchronous downstream channel and a slow asynchronous upstream channel. figure 7 shows a global view of the interface signals of the msc interface. figure 7 general block diag ram of the msc interface the downstream and upstream channels of the msc module communicate with the external world via nine i/o lines. eight output lines are required for the serial communication of the downstream channel (c lock, data, and enable signals). one out of eight input lines sdi[7:0] is used as serial data input signal for the upstream channel. the source of the serial data to be transmi tted by the downstream channel can be msc register contents or data that is provided on the altinl/altinh input lines. these input lines are typically connected with other on-chip peripheral units (for example with a timer unit such as the gpta). an emergency stop in put signal makes it possible to set bits of the serial data stream to dedicated values in an emergency case. clock control, address decoding, and inte rrupt service request control are managed outside the msc module kernel. service reques t outputs are able to trigger an interrupt or a dma request. 4 msc module (kernel) mcb06059 fcln clock control address decoder interrupt control f msc f clc downstream channel upstream channel fclp en0 en1 en2 en3 son sop sdi[7:0] sr[3:0] emgstopmsc altinl[15:0] altinh[15:0] to dma 16 16 8
tc1767 introduction data sheet 35 v1.4, 2012-07 features ? fast synchronous serial interface to connect power switches in particular, or other peripheral devices via serial buses ? high-speed synchronous serial transmission on downstream channel ? serial output clock frequency: f fcl = f msc /2 ? fractional clock divider for precise frequency control of serial clock f msc ? command, data, and passive frame types ? start of serial frame: software-controlled, timer-controlled, or free-running ? programmable upstream data frame length (16 or 12 bits) ? transmission with or without sel bit ? flexible chip select generation indicates status during serial frame transmission ? emergency stop without cpu intervention ? low-speed asynchronous serial reception on upstream channel ? baud rate: f msc divided by 4, 8, 16, 32, 64, 128, or 256 ? standard asynchronous serial frames ? parity error checker ? 8-to-1 input multiplexer for sdi lines ? built-in spike filter on sdi lines ? selectable pin types of do wnstream channel interface: four lvds differential output drivers or four digital gpio pins
tc1767 introduction data sheet 36 v1.4, 2012-07 2.4.4 multican controller the multican module provides two indep endent can nodes in the pg-lqfp-176-5 package, representing two serial communica tion interfaces. the number of available message objects is 64. figure 8 overview of the multican module the multican module contains two indepen dently operating can nodes with full-can functionality that are able to exchange da ta and remote frames via a gateway function. transmission and reception of can fram es is handled in accordance to can specification v2.0 b (active). each can nod e can receive and transmit standard frames with 11-bit identifiers as well as ex tended frames with 29-bit identifiers. all two can nodes share a common set of me ssage objects. each message object can be individually allocated to one of the can nodes. besides serving as a storage container for incoming and outgoing frames , message objects can be combined to build gateways between the can nodes or to set up a fifo buffer. the message objects are organized in doubl e-chained linked lists, where each can node has its own list of message objects. a can node stores frames only into message objects that are allocated to the message object list of the can node, and it transmits only messages belonging to this message obj ect list. a powerful, command-driven list controller performs all messa ge object list operations. multican module kernel mca06060_n2 can node 0 can control message object buffer 64 objects can node 1 txdc0 rxdc0 txdc1 rxdc1 linked list control port control clock control address decoder interrupt control f can f clc
tc1767 introduction data sheet 37 v1.4, 2012-07 the bit timings for the can nodes are derived from the module timer clock ( f can ) and are programmable up to a data rate of 1 mbit /s. external bus transceivers are connected to a can node via a pair of receive and transmit pins. features ? compliant with iso 11898 ? can functionality according to can specification v2.0 b active ? dedicated control registers for each can node ? data transfer rates up to 1 mbit/s ? flexible and powerful message transfer control and error handling capabilities ? advanced can bus bit timing analysis and baud rate detection for each can node via a frame counter ? full-can functionality: a set of 64 message objects can be individually ? allocated (assigned) to any can node ? configured as transmit or receive object ? setup to handle frames with 11-bit or 29-bit identifier ? identified by a timestamp via a frame counter ? configured to remote monitoring mode ? advanced acceptance filtering ? each message object provides an individual acceptance mask to filter incoming frames. ? a message object can be configured to a ccept standard or extended frames or to accept both standard and extended frames. ? message objects can be grouped into four priority classes for transmission and reception. ? the selection of the message to be transmitted first can be based on frame identifier, ide bit and rtr bit according to can arbitration rules, or on its order in the list. ? advanced message object functionality ? message objects can be combined to build fifo message buffers of arbitrary size, limited only by the total number of message objects. ? message objects can be linked to form a gateway that automatically transfers frames between 2 different can buses. a single gateway can link any two can nodes. an arbitrary number of gateways can be defined. ? advanced data management ? the message objects are organized in double-chained lists. ? list reorganizations can be performed at an y time, even during full operation of the can nodes. ? a powerful, command-driven list controller manages the organization of the list structure and ensures consistency of the list. ? message fifos are based on the list structure and can easily be scaled in size during can operation.
tc1767 introduction data sheet 38 v1.4, 2012-07 ? static allocation commands offer compatibility with multican applications that are not list-based. ? advanced interrupt handling ? up to 16 interrupt output lines are available. interrupt requests can be routed individually to one of the 16 interrupt output lines. ? message post-processing noti fications can be combined flexibly into a dedicated register field of 256 notification bits.
tc1767 introduction data sheet 39 v1.4, 2012-07 2.4.5 micro link interface this tc1767 contains one micro link interface, mli0. the micro link interface (mli) is a fast sy nchronous serial interface to exchange data between microcontrollers or other devices, such as stand-alone peripheral components. figure 9 shows how two microcontrollers are typi cally connected together via their mli interfaces. figure 9 typical micro li nk interface connection features ? synchronous serial communication between an mli transmitter and an mli receiver ? different system clock speeds supported in mli transmitter and mli receiver due to full handshake protocol (4 lines between a transmitter and a receiver) ? fully transparent read/write acce ss supported (= remote programming) ? complete address range of target device available ? specific frame protocol to tr ansfer commands, addresses and data ? error detection by parity bit ? 32-bit, 16-bit, or 8-bit data transfers supported ? programmable baud rate: f mli /2 (max. f mli = f sys ) ? address range protection scheme to block unauthorized accesses ? multiple receiving devices supported mca06061 controller 1 cpu peripheral b peripheral a mli system bus controller 2 cpu peripheral d peripheral c mli system bus memory memory
tc1767 introduction data sheet 40 v1.4, 2012-07 figure 10 shows a general block diagram of the mli module. figure 10 general block diag ram of the mli modules the mli transmitter and mli receiver comm unicate with other mli receivers and mli transmitters via a four-line serial connection each. several i/o lines of these connections are available outside the mli module kernel as a four-line output or input vector with index numbering a, b, c and d. the mli module internal i/o control blocks define which signal of a vector is actually taken into account and also allow polarity inversions (to adapt to different physical interconnection means). 4 mcb06062_mod port control tready[d:a] tvalid[d:a] rclk[d:a] mli transmitter mli receiver mli module tdata tclk rready[d:a] rvalid[d:a] rdata[d:a] fract. divider i/o control i/o control move engine sr[7:0] f ml i f sys brkout 4 4 4 4 4 tr[3:0]
tc1767 introduction data sheet 41 v1.4, 2012-07 2.4.6 general purpose timer array (gpta) the tc1767 contains the general purpose timer array (gpta0). figure 11 shows a global view of the gpta module. the gpta provides a set of timer, com pare, and capture functionalities that can be flexibly combined to form signal measurement and signal generation units. they are optimized for tasks typical of engine, gearbox, and electrical motor control applications, but can also be used to generate simple and complex signal waveforms required for other industrial applications. figure 11 general block diagram of the gpta modules in the tc1767 signal generation cells mcb05910_tc1767_ltc 32 gt1 gt0 fpc5 fpc4 fpc3 fpc2 fpc1 fpc0 pdl1 pdl0 dcm2 dcm1 dcm0 digital pll dcm3 gtc02 gtc01 gtc00 gtc31 global timer cell array gtc03 gtc30 cl ock bus gpta0 clock generation cells clock conn . clock distribution cells f gpta ltc 02 ltc 01 ltc 00 ltc 63 local timer cell array ltc 03 ltc 62 ltc02 ltc01 ltc00 ltc31 local timer cell array ltc03 ltc30 ltca2 i/o line sharing block i/o line sharing block interrupt sharing block interrupt sharing block
tc1767 introduction data sheet 42 v1.4, 2012-07 2.4.6.1 functionality of gpta0 the general purpose timer array (gpta0) provides a set of hardware modules required for high-speed digital signal processing: ? filter and prescaler cells (fpc) support input noise filtering and prescaler operation. ? phase discrimination logic units (pdl) dec ode the direction information output by a rotation tracking system. ? duty cycle measurement cells (dc m) provide pulse-width measurement capabilities. ? a digital phase locked loop unit (pll) generates a programmable number of gpta module clock ticks during an input signal?s period. ? global timer units (gt) driven by various clock sources are implemented to operate as a time base for the associated global timer cells. ? global timer cells (gtc) can be programm ed to capture the contents of a global timer on an external or internal event. a gtc may also be used to control an external port pin depending on the result of an in ternal compare operation. gtcs can be logically concatenated to provide a common external port pin with a complex signal waveform. ? local timer cells (ltc) operating in timer, capture, or compare mode may also be logically tied together to drive a common external port pin with a complex signal waveform. ltcs ? enabled in timer mode or capture mode ? can be clocked or triggered by various external or internal events. ? on-chip trigger and gating signals (otgs) can be configured to provide trigger or gating signals to integrated peripherals. input lines can be shared by an ltc and a gtc to trigger their programmed operation simultaneously. the following list summarizes the spec ific features of the gpta units. clock generation unit ? filter and prescaler cell (fpc) ? six independent units ? three basic operating modes: prescaler, delayed debounce filt er, immediate debounce filter ? selectable input sources: port lines, gpta module clock, fpc output of preceding fpc cell ? selectable input clocks: gpta module clock, prescaled gpta modu le clock, dcm clock, compensated or uncompensated pll clock. ? f gpta /2 maximum input signal frequency in filter modes ? phase discriminator logic (pdl) ? two independent units ? two operating modes (2- and 3- sensor signals)
tc1767 introduction data sheet 43 v1.4, 2012-07 ? f gpta /4 maximum input signal frequency in 2-sensor mode, f gpta /6 maximum input signal frequency in 3-sensor mode ? duty cycle measurement (dcm) ? four independent units ? 0 - 100% margin and time-out handling ? f gpta maximum resolution ? f gpta /2 maximum input signal frequency ? digital phase locked loop (pll) ?one unit ? arbitrary multiplication factor between 1 and 65535 ? f gpta maximum resolution ? f gpta /2 maximum input signal frequency ? clock distribution unit (cdu) ?one unit ? provides nine clock output signals: f gpta , divided f gpta clocks, fpc1/fpc4 outputs, dcm clock, ltc prescaler clock signal generation unit ? global timers (gt) ? two independent units ? two operating modes (free-running timer and reload timer) ? 24-bit data width ? f gpta maximum resolution ? f gpta /2 maximum input signal frequency ? global timer cell (gtc) ? 32 units related to the global timers ? two operating modes (capture, compare and capture after compare) ? 24-bit data width ? f gpta maximum resolution ? f gpta /2 maximum input signal frequency ? local timer cell (ltc) ? 64 independent units ? three basic operating modes (timer, capture and compare) for 63 units ? special compare modes for one unit ? 16-bit data width ? f gpta maximum resolution ? f gpta /2 maximum input signal frequency interrupt sharing unit ? 143 interrupt sources, generating up to 46 service requests
tc1767 introduction data sheet 44 v1.4, 2012-07 on-chip trigger unit ? 16 on-chip trigger signals i/o sharing unit ? interconnecting inputs and outputs from inte rnal clocks, fpc, gt c, ltc, ports, and msc interface
tc1767 introduction data sheet 45 v1.4, 2012-07 2.4.7 analog-to-digital converters the tc1767 includes two analog to digital converter modules (adc0, adc1) and one fast analog to digital converter (fadc). 2.4.7.1 adc block diagram the analog to digital converter module (adc) allows the conversion of analog input values into discrete digital values bas ed on the successive approximation method. this module contains 2 independent ke rnels (adc0, adc1) that can operate autonomously or can be synchronized to each other. an adc kernel is a unit used to convert an analog input signal (done by an analog part) and provides means for triggering conversions, data handling and storage (done by a digital part). figure 12 adc module with two adc kernels features of the analog part of each adc kernel: ? input voltage range from 0v to analog supply voltage ? analog supply voltage range from 3.3 v to 5 v (single supply) (5v nominal supply voltage, performance degradation accepted for lower voltages) ? input multiplexer width of 16 possible analog input channels (not all of them are necessarily available on pins) ?v aref and 1 alternative reference input at channel 0 ? programmable sample time (in periods of f adci ) ? wide range of accepted analog clock frequencies f adci adc_2_kernels ad converter analog part kernel 0 conversion control digital part kernel 0 ... analog inputs data (result) handling request control bus inter- face ad converter analog part kernel 1 conversion control digital part kernel 1 ... data (result) handling request control analog inputs
tc1767 introduction data sheet 46 v1.4, 2012-07 ? multiplexer test mode (channel 7 input can be connected to ground via a resistor for test purposes during run time by specific control bit) ? power saving mechanisms features of the digital part of each adc kernel: ? independent result registers (16 independent registers) ? 5 conversion request sources (e.g. for external events, auto-scan, programmable sequence, etc.) ? synchronization of the adc kernels for concurrent conversion starts ? control an external analog multiplexer, respecting the additional set up time ? programmable sampling times for different channels ? possibility to cancel running conversions on demand with automatic restart ? flexible interrupt generation (possibility of dma support) ? limit checking to reduce interrupt load ? programmable data reduction filter by adding conversion results ? support of conversion data fifo ? support of suspend and power down modes ? individually programmable reference selection for each channel (with exception of dedicated channels always referring to v aref )
tc1767 introduction data sheet 47 v1.4, 2012-07 2.4.7.2 fadc short description general features ? extreme fast conversion, 21 cycles of f fadc clock (262.5 ns @ f fadc = 80 mhz) ? 10-bit a/d conversion (higher resolution can be achieved by averaging of consecutive conversions in di gital data reduction filter) ? successive approximation conversion method ? each differential input channel can also be used as single-ended input ? offset calibration support for each channel ? programmable gain of 1, 2, 4, or 8 for each channel ? free-running (channel timers) or triggered conversion modes ? trigger and gating control for external signals ? built-in channel timers for internal triggering ? channel timer request periods independently selectable for each channel ? selectable, programmable digital anti-aliasi ng and data reduction filter block with four independent filter units figure 13 block diagram of the fadc module with 4 input channels as shown in figure 13 , the main fadc functional blocks are: ? an input structure contai ning the differential i nputs and impedance control. srx mcb06065_m4 v fagnd v ddaf v ssaf v ddmf v faref v ssmf interrupt control ts[h:a] gs[h:a] clock control f fadc f clc a/d converter stage data reduction unit fain0p fain0n fain1p fain1n input structure channel trigger control channel timers srx dma a/d control v ddif input channel 0 input channel 1 fain2p fain2n fain3p fain3n input channel 2 input channel 3
tc1767 introduction data sheet 48 v1.4, 2012-07 ? an a/d converter stage responsible for the analog-to-digital conversion including an input multiplexer to select between the channel amplifiers ? a data reduction unit containing progra mmable anti-aliasing and data reduction filters ? a channel trigger control block determining the trigger and gating conditions for the fadc channels ? a channel timer for each channel to independently trigger the conversions ? an a/d control block responsible for the overall fadc functionality fadc power supply and references the fadc module is supplied by the following power supply and reference voltage lines: ?v ddmf / v ssmf : fadc analog channel amplifier power supply (3.3 v) ?v ddif / v ssmf : fadc analog input stage power supply (3.3 - 5 v), the v ddif supply does not appear as supply pin, because it is internally connected to the v ddm supply of the adc that is sharing the fadc input pins. ?v ddaf / v ssaf : fadc analog part power supply (1.5 v), to be fed in externally ?v faref / v fagnd : fadc reference voltage (3.3 v max.) and fadc reference ground input structure the input structure of the fadc in the tc1767 contains: ? a differential analog input stage for each input channel to select the input impedance (differential or single-ended measuremen t) and to decouple the fadc input signal from the pins. ? a channel amplifier for each input channel with a settling time (about 5s) when changing the characteristics of an input stage (changing between unused, differential, single-ended n, or single-ended p mode).
tc1767 introduction data sheet 49 v1.4, 2012-07 figure 14 fadc input structure in tc1767 2.5 on-chip debug support (ocds) the tc1767 contains resources for different kinds of ?debugging?, covering needs from software development to real-time-tuning. these resources are either embedded in specific modules (e.g. breakpoint logic of the tricore) or part of a central peripheral (known as cerberus). 2.5.1 on-chip debug support the classic software debug approach (sta rt/stop, single-stepping) is supported by several features labelled ?ocds level 1?: ? run/stop and single-step execution independently for tricore and pcp. ? means to request all kinds of reset without usage of sideband pins. ? halt-after-reset for repeatable debug sessions. mca06432_m4n fain0n fain0p analog input stages rp rn channel amplifier stages gain a/d a/d control conversion control converter stage chnr v ddaf v ssaf fain2n fain2p rp rn fain1n fain1p rp rn v ddif fain3n fain3p rp rn v ssmf v ssmf v ddmf v ssmf v ddmf v ssmf v ddmf v ssmf v ddmf
tc1767 introduction data sheet 50 v1.4, 2012-07 ? different boot modes to use application so ftware not yet programmed to the flash. ? a total of four hardware breakpoints for the tricore based on instruction address, data address or combination of both. ? unlimited number of software breakpoints (debug instruction) for tricore and pcp . ? debug event generated by access to a spec ific address via t he system peripheral bus. ? tool access to all sfrs and internal memories independent of the cores. ? two central break switches to collect debug events from all modules (tricore, pcp, dma, bcu, break input pins) and distribut e them selectively to breakable modules (tricore, pcp, break output pins). ? central suspend switch to suspend parts of the system (tricore , pcp, peripherals) instead if breaking them as reaction to a debug event. ? dedicated interrupt resources to handle debug events inside tricore (breakpoint trap, software interrupt) and cerberus (can trigger pcp), e.g. for implementing monitor programs. ? access to all ocds level 1 resources also for tricore and pcp themselvesitself for debug tools integrated into the application code. ? triggered transfer of data in response to a debug event; if target is programmed to be a device interface simple variable tracing can be done. additionally, in depth performance analysis and profiling support is provided by the emulation device through mcds event counters driven by a variety of trigger signals (e.g. cache hit, wait state, interrupt accepted). 2.5.2 real time trace for detailed tracing of the system?s behavio r a pin-compatible emulation device is available. 1) 2.5.3 calibration support two main use cases are catered for by resources in addition the ocds level 1 infrastructure: overlay of non-volatile on -chip memory and non-intrusive signaling: ? 8 kb sram for overlay. ? can be split into up to 16 blocks which can overlay independent regions of on-chip data flash. ? changing the configuration is triggered by a single sfr access to maintain consistency. ? overlay configuration switch does not require the tricore to be stopped or suspended. 1) the ocds l2 interface of audong is not available.
tc1767 introduction data sheet 51 v1.4, 2012-07 ? invalidation of the data cache (maintaining write-back data) can be done concurrently with the same sfr. ? 256 kb additional overlay ram on emulation device. ? the 256 kb trace memory of the emulat ion device can optionally be used for overlay also. ? a dedicated trigger sfr with 32 independent st atus bits is provid ed to centrally post requests from application code to the host computer. ? the host is notified automatically when the trigger sfr is updated by the tricore or pcp. no polling via a system bus is required. 2.5.4 tool interfaces three options exist for the communication channel between tools (e.g. debugger, calibration tool) and tc1767: ? two wire dap (device access port) pr otocol for long connections or noisy environments. ? four (or five) wire jtag (ieee 1149.1) for standardized manufacturing tests. ? can (plus software linked into the ap plication code) for low bandwidth deeply embedded purposes. ? dap and jtag are clocked by the tool. ? bit clock up to 40 mhz for jtag, up to 80 mhz for dap. ? hot attach (i.e. physical disconnect/reconn ect of the host connection without reset of the tc1767) for all interfaces. ? infineon standard das (device access server) implementation for seamless, transparent tool access ov er any supported interface. ? lock mechanism to prevent unauthorized to ol access to critical application code. 2.5.5 self-test support some manufacturing tests can be invoked by the application (e.g. after power-on) if needed: ? hardware-accelerated checksum calc ulation (e.g. fo r flash content). 2.5.6 far support to efficiently locate and identify faults after integratio n of a tc1767 into a system special functions are available: ? boundary scan (ieee 1149 .1) via jtag and dap. ? sscm (single scan chain mode 1) ) for structural scan test ing of the chip itself. 1) this function requires access to some device pins (e.g. testmode ) in addition to those needed for ocds.
tc1767 pinning data sheet 52 v1.4, 2012-07 3 pinning 3.1 tc1767 pin definition and functions figure 15 shows the logic symbol of the device. figure 15 tc1767 logic symbol for the package variant pg-lqfp-176-5. testmode esr0 porst digital circuitry power supply general control an[35:0] analog inputs v ddm v ssm v ddmf v ssmf v ddaf v ar ef0 v agnd0 v faref v fagnd v ddfl3 analog power supply tc 1767_logsym_176 v ddosc3 alternate functions oscillator gpta, scu gpta, ssc0/1, mli 0, msc0 gpta, asc0/1, ssc0/1, scu, can gpta, scu v ddosc gpta, mli0 v ssosc tc1767 pg-lqfp- 176 -x port 0 16 port 1 16 port 2 14 port 3 16 port 4 4 port 5 16 port 6 4 gpta, msc0 xtal2 xtal1 v ss 11 v ddp 10 v dd 9 esr1 trst tck / dap0 tdi / brkin tdo / dap2 / brkout tms / dap1 ocds / jtag control gpta, ssc1, adc0, ocds
tc1767 pinning data sheet 53 v1.4, 2012-07 3.1.1 tc1767 pin configuration: pg-lqfp-176-5 this chapter shows the pin configuratio n of the package variant pg-lqfp-176-5 1) . figure 16 tc1767 pinning for pg-lqfp-176-5 1) tc1767 ed: pg-lqfp-176-6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 39 40 41 42 43 44 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 30 31 32 33 34 35 36 37 38 45 46 47 48 49 50 51 52 53 97 96 95 94 93 92 91 90 89 100 99 98 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 13 3 13 4 13 5 13 6 137 13 8 13 9 14 0 14 1 14 2 14 3 14 4 14 5 14 6 147 14 8 14 9 15 0 15 1 15 2 15 3 15 4 15 5 15 6 157 15 8 15 9 16 0 16 1 16 2 16 3 16 4 16 5 16 6 167 16 8 16 9 17 0 17 1 17 2 173 174 175 176 p0 .0 /i n0 /h wc fg0 /o ut0 / ou t5 6 p0 .1 /i n1 /h wc fg1 /o ut1 / ou t5 7 p0 .2 /i n2 /h wc fg2 /o ut2 / ou t5 8 p0 .3 /i n3 /h wc fg3 /o ut3 / ou t5 9 p0 .4 /i n4 /h wc fg4 /o ut4 / ou t6 0 p0 .5 /i n5 /h wc fg5 /o ut5 / ou t6 1 p0 .6 /i n6 /h wc fg6 /r eq2/ out6 /ou t6 2 p0 .7 /i n7 /h wc fg7 /r eq3/ out7 /ou t6 3 p0 .8 /i n8 /o u t8/ out6 4 p0 .9 /i n9 /o u t9/ out6 5 p0.10/in10/out10/out66 p0.11/in11/out11/out67 p0.12/in12/out12/out68 p0.13/in13/out13/out69 p0.14/in14/req4/out14/out70 p0.15/in15/req5/out15/out71 p1.0/in16/out16/out72/brkin/brkout p1 .1 5 /br kin /br kou t p1.2/in18/out18/out74 p1.3/in19/out19/out75 p1.4/in20/emgstop/out20/out76 p1.5/in21/out21/out77 p1.6/in22/out22/out78 p1.7/in23/out23/out79 p1 .8 /in 2 4 /in 4 8 /mtsr 1 b/o u t2 4 /o u t4 8 p1 .9 /in 2 5 /in 4 9 /mr st1 b/o u t2 5 /o u t4 9 p1.10/in26/in50/out26/out50/slso17 p1.11/in27/in51/sclk1b/out27/out51 ad0emux0/out16/in16/p1.12 ad0emux1/out17/in17/p1.13 ad0emux2/out18/in18/p1.14 tclk0/out28/out32/in32/p2.0 sl so1 3/ sl so0 3/ out3 3 /tr ead y0 a/ in3 3 /p 2. 1 tvalid0a/out29/out34/in34/p2.2 tdat a0/out30/out35/in35/p2.3 out31/out36/rclk0a/in36/p2.4 rready0a/out37/out110/in37/p2.5 out38/out111/rvalid0a/in38/p2.6 out3 9 /r da ta0 a/ in3 9 /p 2. 7 p2.8/slso04/slso14/en00 p2.9/slso05/slso15/en01 p2.10/in10/out0/mrst1a p2.11/in11/out1/sclk1a/fclp0b p2.12/in12/out2/mtsr1a/sop0b p2.13/in13/out3/slsi11/sdi0 p3.0out84//rxd0a p3.1out85//txd0 p3 .2 /o u t8 6 /sc l k0 p3 .3 /o u t8 7 /mr st0 p3 .4 /o u t8 8 /mtsr 0 p3.5/slso00/slso10/slso00&slso10 p3.6/slso01/slso11/slso01&slso11 p3.7/slsi01/out89//slso02/slso12 p3.8/slso06/out90/txd1 p3 .9 /ou t91 /r xd 1 a p3.10/out92/req0 p3.11/out93//req1 p3.12/out94//rxdcan0/rxd0b p3.13/out95//txdcan0/txd0 p3.14/out96rxdcan1/rxd1b p3.15/out97/txdcan1/txd1 out52/out28/in52/in28/p4.0 out53/out29/in53/in29/p4.1 extc l k1 /o u t54 /o u t3 0/ in 54 / in3 0 /p 4. 2 p4 .3 /in 3 1 /in 5 5 /o u t3 1 /o u t5 5 /extc l k0 out40/out8/in40/in26/p5.0 out41/out9/in41/in27/p5.1 out42/out10/in42/in28/p5.2 out44/out12/in44/in29/p5.4 out43/out11/in43/p5.3 out45/out13/in45/in30/p5.5 out46/out14/in46/in31/p5.6 out47/out15/in47/p5.7 tclk0/out95/p5.15 r val id 0 b/o u t9 0 /p5 .9 r r ead y0b/ou t91 /p5.1 0 rclk0b/out92/p5.11 tdata0/slso07/out93/p5.12 tvalid0b/slso16/p5.13 tready0b/out94/p5.14 rdata0b/out89/p5.8 p6.1/in15/out5/out81/fclp0a p6.0/in14/out4/out80/fcln0 p6.3/in25/out7/out83/sop0a p6.2/in24/out6/out82/son0 an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 8 an 7 an 9 an 1 0 an 1 1 an 1 2 an 1 3 an 1 4 an 1 5 an 1 6 an 1 7 an 1 8 an 1 9 an 2 0 an 2 1 an 2 2 an 2 3 an 2 4 an 2 5 an 2 6 an 2 7 an 2 8 an 2 9 an 3 0 an 3 1 an 3 2 an 3 3 an 3 4 an 3 5 trst p1.1/in17/out17/out73 td i/br kin /br kou t td o /d ap2 /br kin /br ko u t tms/d ap1 tc k/d ap0 esr 1 por st v ss testmod e xtal 1 xtal 2 v dd v ddp v ss v ddp v dd(sb) tc1767 v dd v ddp v ss v ddm f v ssm f v ddaf v ss v faref v fag nd v dd m v ssm v are f0 v ag nd 0 v dd v ddp v ss v dd v ddp v ss v ss v dd v ddp v ss v ddo sc v ddo sc3 v sso sc v ddfl 3 v ddp v ss v dd v ddp v ss v dd v ddp v ss mcp06067 v ddp v dd esr 0
tc1767 pinning data sheet 54 v1.4, 2012-07 table 4 pin definitions and functions (pg-lqfp-176-5 package 1) ) pin symbol ctrl. type function port 0 145 p0.0 i/o0 a1/ pu port 0 general purpose i/o line 0 in0 i gpta0 input 0 in0 i ltca2 input 0 hwcfg0 i hardware configuration input 0 out0 o1 gpta0 output 0 out56 o2 gpta0 output 56 out0 o3 ltca2 output 0 146 p0.1 i/o0 a1/ pu port 0 general purpose i/o line 1 in1 i gpta0 input 1 in1 i ltca2 input 1 hwcfg1 i hardware configuration input 1 out1 o1 gpta0 output 1 out57 o2 gpta0 output 57 out1 o3 ltca2 output 1 147 p0.2 i/o0 a1/ pu port 0 general purpose i/o line 2 in2 i gpta0 input 2 in2 i ltca2 input 2 hwcfg2 i hardware configuration input 2 out2 o1 gpta0 output 2 out58 o2 gpta0 output 58 out2 o3 ltca2 output 2 148 p0.3 i/o0 a1/ pu port 0 general purpose i/o line 3 in3 i gpta0 input 3 in3 i ltca2 input 3 hwcfg3 i hardware configuration input 3 out3 o1 gpta0 output 3 out59 o2 gpta0 output 59 out3 o3 ltca2 output 3
tc1767 pinning data sheet 55 v1.4, 2012-07 166 p0.4 i/o0 a1/ pu port 0 general purpose i/o line 4 in4 i gpta0 input 4 in4 i ltca2 input 4 hwcfg4 i hardware configuration input 4 out4 o1 gpta0 output 4 out60 o2 gpta0 output 60 out4 o3 ltca2 output 4 167 p0.5 i/o0 a1/ pu port 0 general purpose i/o line 5 in5 i gpta0 input 5 in5 i ltca2 input 5 hwcfg5 i hardware configuration input 5 out5 o1 gpta0 output 5 out61 o2 gpta0 output 61 out5 o3 ltca2 output 5 173 p0.6 i/o0 a1/ pu port 0 general purpose i/o line 6 in6 i gpta0 input 6 in6 i ltca2 input 6 hwcfg6 i hardware configuration input 6 req2 i external request input 2 out6 o1 gpta0 output 6 out62 o2 gpta0 output 62 out6 o3 ltca2 output 6 174 p0.7 i/o0 a1/ pu port 0 general purpose i/o line 7 in7 i gpta0 input 7 in7 i ltca2 input 7 hwcfg7 i hardware configuration input 7 req3 i external request input 3 out7 o1 gpta0 output 7 out63 o2 gpta0 output 63 out7 o3 ltca2 output 7 table 4 pin definitions and functions (pg-lqfp-176-5 package 1) ) (cont?d) pin symbol ctrl. type function
tc1767 pinning data sheet 56 v1.4, 2012-07 149 p0.8 i/o0 a1/ pu port 0 general purpose i/o line 8 in8 i gpta0 input 8 in8 i ltca2 input 8 out8 o1 gpta0 output 8 out64 o2 gpta0 output 64 out8 o3 ltca2 output 8 150 p0.9 i/o0 a1/ pu port 0 general purpose i/o line 9 in9 i gpta0 input 9 in9 i ltca2 input 9 out9 o1 gpta0 output 9 out65 o2 gpta0 output 65 out9 o3 ltca2 output 9 151 p0.10 i/o0 a1/ pu port 0 general purpose i/o line 10 in10 i gpta0 input 10 out10 o1 gpta0 output 10 out66 o2 gpta0 output 66 out10 o3 ltca2 output 10 152 p0.11 i/o0 a1/ pu port 0 general purpose i/o line 11 in11 i gpta0 input 11 out11 o1 gpta0 output 11 out67 o2 gpta0 output 67 out11 o3 ltca2 output 11 168 p0.12 i/o0 a1/ pu port 0 general purpose i/o line 12 in12 i gpta0 input 12 out12 o1 gpta0 output 12 out68 o2 gpta0 output 68 out12 o3 ltca2 output 12 table 4 pin definitions and functions (pg-lqfp-176-5 package 1) ) (cont?d) pin symbol ctrl. type function
tc1767 pinning data sheet 57 v1.4, 2012-07 169 p0.13 i/o0 a1/ pu port 0 general purpose i/o line 13 in13 i gpta0 input 13 out13 o1 gpta0 output 13 out69 o2 gpta0 output 69 out13 o3 ltca2 output 13 175 p0.14 i/o0 a1/ pu port 0 general purpose i/o line 14 in14 i gpta0 input 14 req4 i external request input 4 out14 o1 gpta0 output 14 out70 o2 gpta0 output 70 out14 o3 ltca2 output 14 176 p0.15 i/o0 a1/ pu port 0 general purpose i/o line 15 in15 i gpta0 input 15 req5 i external request input 5 out15 o1 gpta0 output 15 out71 o2 gpta0 output 71 out15 o3 ltca2 output 15 port 1 116 p1.0 i/o0 a2/ pu port 1 general purpose i/o line 0 in16 i gpta0 input 16 brkin i break input out16 o1 gpta0 output 16 out72 o2 gpta0 output 72 out16 o3 ltca2 output 16 brkout o break output (controlled by ocds module) 119 p1.1 i/o0 a1/ pu port 1 general purpose i/o line 1 in17 i gpta0 input 17 out17 o1 gpta0 output 17 out73 o2 gpta0 output 73 out17 o3 ltca2 output 17 table 4 pin definitions and functions (pg-lqfp-176-5 package 1) ) (cont?d) pin symbol ctrl. type function
tc1767 pinning data sheet 58 v1.4, 2012-07 93 p1.2 i/o0 a1/ pu port 1 general purpose i/o line 2 in18 i gpta0 input 18 out18 o1 gpta0 output 18 out74 o2 gpta0 output 74 out18 o3 ltca2 output 18 98 p1.3 i/o0 a1/ pu port 1 general purpose i/o line 3 in19 i gpta0 input 19 in19 i ltca2 input 19 out19 o1 gpta0 output 19 out75 o2 gpta0 output 75 out19 o3 ltca2 output 19 107 p1.4 i/o0 a1/ pu port 1 general purpose i/o line 4 in20 i gpta0 input 20 in20 i ltca2 input 20 emgstop i emergency stop input out20 o1 gpta0 output 20 out76 o2 gpta0 output 76 out20 o3 ltca2 output 20 108 p1.5 i/o0 a1/ pu port 1 general purpose i/o line 35 in21 i gpta0 input 21 in21 i ltca2 input 21 out21 o1 gpta0 output 21 out77 o2 gpta0 output 77 out21 o3 ltca2 output 21 109 p1.6 i/o0 a1/ pu port 1 general purpose i/o line 6 in22 i gpta0 input 22 in22 i ltca2 input 22 out22 o1 gpta0 output 22 out78 o2 gpta0 output 78 out22 o3 ltca2 output 22 table 4 pin definitions and functions (pg-lqfp-176-5 package 1) ) (cont?d) pin symbol ctrl. type function
tc1767 pinning data sheet 59 v1.4, 2012-07 110 p1.7 i/o0 a1/ pu port 1 general purpose i/o line 7 in23 i gpta0 input 23 in23 i ltca2 input 23 out23 o1 gpta0 output 23 out79 o2 gpta0 output 79 out23 o3 ltca2 output 23 94 p1.8 i/o0 a2/ pu port 1 general purpose i/o line 8 in24 i gpta0 input 24 in48 i gpta0 input 48 mtsr1b i ssc1 slave receive input b (slave mode) out24 o1 gpta0 output 24 out48 o2 gpta0 output 48 mtsr1b o3 ssc1 master transmit output b (master mode) 95 p1.9 i/o0 a2/ pu port 1 general purpose i/o line 9 in25 i gpta0 input 25 in49 i gpta0 input 49 mrst1b i ssc1 master receive input b (master mode) out25 o1 gpta0 output 25 out49 o2 gpta0 output 49 mrst1b o3 ssc1 slave transmit output b (slave mode) 96 p1.10 i/o0 a2/ pu port 1 general purpose i/o line 10 in26 i gpta0 input 26 in50 i gpta0 input 50 out26 o1 gpta0 output 26 out50 o2 gpta0 output 50 slso17 o3 ssc1 slave select output 7 table 4 pin definitions and functions (pg-lqfp-176-5 package 1) ) (cont?d) pin symbol ctrl. type function
tc1767 pinning data sheet 60 v1.4, 2012-07 97 p1.11 i/o0 a2/ pu port 1 general purpose i/o line 11 in27 i gpta0 input 27 in51 i gpta0 input 51 sclk1b i ssc1 clock input b out27 o1 gpta0 output 27 out51 o2 gpta0 output 51 sclk1b o3 ssc1 clock output b 73 p1.12 i/o0 a1/ pu port 1 general purpose i/o line 12 in16 i ltca2 input 16 ad0emux0 o1 adc0 external multiplexer control output 0 ad0emux0 o2 adc0 external multiplexer control output 0 out16 o3 ltca2 output 16 72 p1.13 i/o0 a1/ pu port 1 general purpose i/o line 13 in17 i ltca2 input 17 ad0emux1 o1 adc0 external multiplexer control output 1 ad0emux1 o2 adc0 external multiplexer control output 1 out17 o3 ltca2 output 17 71 p1.14 i/o0 a1/ pu port 1 general purpose i/o line 14 in18 i ltca2 input 18 ad0emux2 o1 adc0 external multiplexer control output 2 ad0emux2 o2 adc0 external multiplexer control output 2 out18 o3 ltca2 output 18 117 p1.15 i/o0 a2/ pu port 1 general purpose i/o line 15 brkin i break input reserved o1 - reserved o2 - reserved o3 - brkout o break output (controlled by ocds module) port 2 table 4 pin definitions and functions (pg-lqfp-176-5 package 1) ) (cont?d) pin symbol ctrl. type function
tc1767 pinning data sheet 61 v1.4, 2012-07 74 p2.0 i/o0 a2/ pu port 2 general purpose i/o line 0 in32 i gpta0 input 32 out32 o1 gpta0 output 32 tclk0 o2 mli0 transmitter clock output 0 out28 o3 ltca2 output 28 75 p2.1 i/o0 a2/ pu port 2 general purpose i/o line 1 in33 i gpta0 input 33 tready0a i mli0 transmitter ready input a out33 o1 gpta0 output 33 slso03 o2 ssc0 slave select output line 3 slso13 o3 ssc1 slave select output line 3 76 p2.2 i/o0 a2/ pu port 2 general purpose i/o line 2 in34 i gpta0 input 34 out34 o1 gpta0 output 34 tvalid0 o2 mli0 transmitter valid output out29 o3 ltca2 output 29 77 p2.3 i/o0 a2/ pu port 2 general purpose i/o line 3 in35 i gpta0 input 35 out35 o1 gpta0 output 35 tdata0 o2 mli0 transmitter data output out30 o3 ltca2 output 30 78 p2.4 i/o0 a2/ pu port 2 general purpose i/o line 4 in36 i gpta0 input 36 rclk0a i mli receiver clock input a out36 o1 gpta0 output 36 out36 o2 gpta0 output 36 out31 o3 ltca2 output 31 table 4 pin definitions and functions (pg-lqfp-176-5 package 1) ) (cont?d) pin symbol ctrl. type function
tc1767 pinning data sheet 62 v1.4, 2012-07 79 p2.5 i/o0 a2/ pu port 2 general purpose i/o line 5 in37 i gpta0 input 37 out37 o1 gpta0 output 37 rready0a o2 mli0 receiver ready output a out110 o3 ltca2 output 110 80 p2.6 i/o0 a2/ pu port 2 general purpose i/o line 6 in38 i gpta0 input 38 rvalid0a i mli receiver valid input a out38 o1 gpta0 output 38 out38 o2 gpta0 output 38 out111 o3 ltca2 output 111 81 p2.7 i/o0 a2/ pu port 2 general purpose i/o line 7 in39 i gpta0 input 39 rdata0a i mli receiver data input a out39 o1 gpta0 output 39 out39 o2 gpta0 output 39 reserved o3 - 164 p2.8 i/o0 a2/ pu port 2 general purpose i/o line 8 slso04 o1 ssc0 slave select output 4 slso14 o2 ssc1 slave select output 4 en00 o3 msc0 enable output 0 160 p2.9 i/o0 a2/ pu port 2 general purpose i/o line 9 slso05 o1 ssc0 slave select output 5 slso15 o2 ssc1 slave select output 5 en01 o3 msc0 enable output 1 table 4 pin definitions and functions (pg-lqfp-176-5 package 1) ) (cont?d) pin symbol ctrl. type function
tc1767 pinning data sheet 63 v1.4, 2012-07 161 p2.10 i/o0 a2/ pu port 2 general purpose i/o line 10 mrst1a i ssc1 master receive input a in10 i ltca2 input 10 mrst1a o1 ssc1 slave transmit output out0 o2 ltca2 output 0 reserved o3 - 162 p2.11 i/o0 a2/ pu port 2 general purpose i/o line 11 sclk1a i ssc1 clock input a in11 i ltca2 input 11 sclk1a o1 ssc1 clock output a out1 o2 ltca2 output 1 fclp0b o3 msc0 clock outp ut positive b 163 p2.12 i/o0 a2/ pu port 2 general purpose i/o line 12 mtsr1a i ssc1 slave receive input a in12 i ltca2 input 12 mtsr1a o1 ssc1 master transmit output a out2 o2 ltca2 output 2 sop0b o3 msc0 serial data output positive b 165 p2.13 i/o0 a1/ pu port 2 general purpose i/o line 13 slsi11 i ssc1 slave select input 1 sdi0 i msc0 serial data input in13 i ltca2 input 13 out3 o1 ltca2 output 3 reserved o2 - reserved o3 - port 3 table 4 pin definitions and functions (pg-lqfp-176-5 package 1) ) (cont?d) pin symbol ctrl. type function
tc1767 pinning data sheet 64 v1.4, 2012-07 136 p3.0 i/o0 a1/ pu port 3 general purpose i/o line 0 rxd0a i asc0 receiver input a (async. & sync. mode) rxd0a o1 asc0 output (sync. mode) rxd0a o2 asc0 output (sync. mode) out84 o3 gpta0 output 84 135 p3.1 i/o0 a1/ pu port 3 general purpose i/o line 1 txd0 o1 asc0 output txd0 o2 asc0 output out85 o3 gpta0 output 85 129 p3.2 i/o0 a2/ pu port 3 general purpose i/o line 2 sclk0 i ssc0 clock input (slave mode) sclk0 o1 ssc0 clock output (master mode) sclk0 o2 ssc0 clock input (master mode) out86 o3 gpta0 output 86 130 p3.3 i/o0 a2/ pu port 3 general purpose i/o line 3 mrst0 i ssc0 master receive input (master mode) mrst0 o1 ssc0 slave transmit output (slave mode) mrst0 o2 ssc0 slave transmit output (slave mode) out87 o3 gpta0 output 87 132 p3.4 i/o0 a2/ pu port 3 general purpose i/o line 4 mtsr0 i ssc0 slave receive input (slave mode) mtsr0 o1 ssc0 master transmit output (master mode) mtsr0 o2 ssc0 master transmit output (master mode) out88 o3 gpta0 output 88 126 p3.5 i/o0 a2/ pu port 3 general purpose i/o line 5 slso00 o1 ssc0 slave select output 0 slso10 o2 ssc1 slave select output 0 slsoando0 o3 ssc0 and ssc1 slave select output 0 table 4 pin definitions and functions (pg-lqfp-176-5 package 1) ) (cont?d) pin symbol ctrl. type function
tc1767 pinning data sheet 65 v1.4, 2012-07 127 p3.6 i/o0 a2/ pu port 3 general purpose i/o line 6 slso01 o1 ssc0 slave select output 1 slso11 o2 ssc1 slave select output 1 slsoando1 o3 ssc0 and ssc1 slave select output 1 131 p3.7 i/o0 a2/ pu port 3 general purpose i/o line 7 slsi01 i ssc0 slave select input 1 slso02 o1 ssc0 slave select output 2 slso12 o2 ssc1 slave select output 2 out89 o3 gpta0 output 89 128 p3.8 i/o0 a2/ pu port 3 general purpose i/o line 8 slso06 o1 ssc0 slave select output 6 txd1 o2 asc1 transmit output out90 o3 gpta0 output 90 138 p3.9 i/o0 a1/ pu port 3 general purpose i/o line 9 rxd1a i asc1 receiver input a rxd1a o1 asc1 receiver output a (synchronous mode) rxd1a o2 asc1 receiver output a (synchronous mode) out91 o3 gpta0 output 91 137 p3.10 i/o0 a1/ pu port 3 general purpose i/o line 10 req0 i external request input 0 reserved o1 - reserved o2 - out92 o3 gpta0 output 92 144 p3.11 i/o0 a1/ pu port 3 general purpose i/o line 11 req1 i external request input 1 reserved o1 - reserved o2 - out93 o3 gpta0 output 93 table 4 pin definitions and functions (pg-lqfp-176-5 package 1) ) (cont?d) pin symbol ctrl. type function
tc1767 pinning data sheet 66 v1.4, 2012-07 143 p3.12 i/o0 a1/ pu port 3 general purpose i/o line 12 rxdcan0 i can node 0 receiver input rxd0b i asc0 receiver input b rxd0b o1 asc0 receiver output b (synchronous mode) rxd0b o2 asc0 receiver output b (synchronous mode) out94 o3 gpta0 output 94 142 p3.13 i/o0 a2/ pu port 3 general purpose i/o line 13 txdcan0 o1 can node 0 transmitter output txd0 o2 asc0 transmit output out95 o3 gpta0 output 95 134 p3.14 i/o0 a1/ pu port 3 general purpose i/o line 14 rxdcan1 i can node 1 receiver input rxd1b i asc1 receiver input b rxd1b o1 asc1 receiver output b (synchronous mode) rxd1b o2 asc1 receiver output b (synchronous mode) out96 o3 gpta0 output 96 133 p3.15 i/o0 a2/ pu port 3 general purpose i/o line 15 txdcan1 o1 can node 1 transmitter output txd1 o2 asc1 transmit output out97 o3 gpta0 output 97 port 4 86 p4.0 i/o0 a1/ pu port 4 general purpose i/o line 0 in28 i gpta0 input 28 in52 i gpta0 input 52 out28 o1 gpta0 output 28 out52 o2 gpta0 output 52 reserved o3 - table 4 pin definitions and functions (pg-lqfp-176-5 package 1) ) (cont?d) pin symbol ctrl. type function
tc1767 pinning data sheet 67 v1.4, 2012-07 87 p4.1 i/o0 a1/ pu port 4 general purpose i/o line 1 in29 i gpta0 input 29 in53 i gpta0 input 53 out29 o1 gpta0 output 29 out53 o2 gpta0 output 53 reserved o3 - 88 p4.2 i/o0 a2/ pu port 4 general purpose i/o line 2 in30 i gpta0 input 30 in54 i gpta0 input 54 out30 o1 gpta0 output 30 out54 o2 gpta0 output 54 extclk1 o3 external clock 1 output 90 p4.3 i/o0 a2/ pu port 4 general purpose i/o line 3 in31 i gpta0 input 31 in55 i gpta0 input 55 out31 o1 gpta0 output 31 out55 o2 gpta0 output 55 extclk0 o3 external clock 0 output port 5 1 p5.0 i/o0 a1/ pu port 5 general purpose i/o line 0 in40 i gpta0 input 40 in26 i ltca2 input 26 out40 o1 gpta0 output 40 out8 o2 ltca2 output 8 reserved o3 - table 4 pin definitions and functions (pg-lqfp-176-5 package 1) ) (cont?d) pin symbol ctrl. type function
tc1767 pinning data sheet 68 v1.4, 2012-07 2 p5.1 i/o0 a1/ pu port 5 general purpose i/o line 1 in41 i gpta0 input 41 in27 i ltca2 input 27 out41 o1 gpta0 output 41 out9 o2 ltca2 output 9 reserved o3 - 3 p5.2 i/o0 a1/ pu port 5 general purpose i/o line 2 in42 i gpta0 input 42 in28 i ltca2 input 28 out42 o1 gpta0 output 42 out10 o2 ltca2 output 10 reserved o3 - 4 p5.3 i/o0 a1/ pu port 5 general purpose i/o line 3 in43 i gpta0 input 43 out43 o1 gpta0 output 43 out11 o2 ltca2 output 11 reserved o3 - 5 p5.4 i/o0 a1/ pu port 5 general purpose i/o line 4 in44 i gpta0 input 44 in29 i ltca2 input 29 out44 o1 gpta0 output 44 out12 o2 ltca2 output 12 reserved o3 - 6 p5.5 i/o0 a1/ pu port 5 general purpose i/o line 5 in45 i gpta0 input 45 in30 i ltca2 input 30 out45 o1 gpta0 output 45 out13 o2 ltca2 output 13 reserved o3 - table 4 pin definitions and functions (pg-lqfp-176-5 package 1) ) (cont?d) pin symbol ctrl. type function
tc1767 pinning data sheet 69 v1.4, 2012-07 7 p5.6 i/o0 a1/ pu port 5 general purpose i/o line 6 in46 i gpta0 input 46 in31 i ltca2 input 31 out46 o1 gpta0 output 46 out14 o2 ltca2 output 14 reserved o3 - 8 p5.7 i/o0 a1/ pu port 5 general purpose i/o line 7 in47 i gpta0 input 47 out47 o1 gpta0 output 47 out15 o2 ltca2 output 15 reserved o3 - 13 p5.8 i/o0 a2/ pu port 5 general purpose i/o line 8 rdata0b i mli0 receiver data input b reserved o1 - reserved o2 - out89 o3 ltca2 output 89 14 p5.9 i/o0 a2/ pu port 5 general purpose i/o line 9 rvalid0b i mli0 receiver data valid input b reserved o1 - reserved o2 - out90 o3 ltca2 output 90 15 p5.10 i/o0 a2/ pu port 5 general purpose i/o line 10 rready0b o1 mli0 receiver ready input b reserved o2 - out91 o3 ltca2 output 91 16 p5.11 i/o0 a2/ pu port 5 general purpose i/o line 11 rclk0b i mli0 receiver clock input b reserved o1 - reserved o2 - out92 o3 ltca2 output 92 table 4 pin definitions and functions (pg-lqfp-176-5 package 1) ) (cont?d) pin symbol ctrl. type function
tc1767 pinning data sheet 70 v1.4, 2012-07 17 p5.12 i/o0 a2/ pu port 5 general purpose i/o line 12 tdata0 o1 mli0 transmitter data output slso07 o2 ssc0 slave select output 7 out93 o3 ltca2 output 93 18 p5.13 i/o0 a2/ pu port 5 general purpose i/o line 13 tvalid0b o1 mli0 transmitter valid input b slso16 o2 ssc1 slave select output 6 reserved o3 - 19 p5.14 i/o0 a2/ pu port 5 general purpose i/o line 14 tready0b i mli0 transmitter ready input b reserved o1 - reserved o2 - out94 o3 ltca2 output 94 9 p5.15 i/o0 a2/ pu port 5 general purpose i/o line 15 tclk0 o1 mli0 transmitter clock output reserved o2 - out95 o3 ltca2 output 95 port 6 156 p6.0 i/o0 a1/ f/ pu port 6 general purpose i/o line 0 in14 i ltca2 input 14 fcln0 o1 msc0 clock output negative out80 o2 gpta0 output 80 out4 o3 ltca2 output 4 157 p6.1 i/o0 a1/ f/ pu port 6 general purpose i/o line 1 in15 i ltca2 input 15 fclp0a o1 msc0 clock outp ut positive a out81 o2 gpta0 output 81 out5 o3 ltca2 output 5 table 4 pin definitions and functions (pg-lqfp-176-5 package 1) ) (cont?d) pin symbol ctrl. type function
tc1767 pinning data sheet 71 v1.4, 2012-07 158 p6.2 i/o0 a1/ f/ pu port 6 general purpose i/o line 2 in24 i ltca2 input 24 son0 o1 msc0 serial data output negative out82 o2 gpta0 output 82 out6 o3 ltca2 output 6 159 p6.3 i/o0 a1/ f/ pu port 6 general purpose i/o line 3 in25 i ltca2 input 25 sop0a o1 msc0 serial data output positive a out83 o2 gpta0 output 83 out7 o3 ltca2 output 7 analog input port 67 an0 i d analog input 0 66 an1 i d analog input 1 65 an2 i d analog input 2 64 an3 i d analog input 3 63 an4 i d analog input 4 62 an5 i d analog input 5 61 an6 i d analog input 6 36 an7 i d analog input 7 60 an8 i d analog input 8 59 an9 i d analog input 9 58 an10 i d analog input 10 57 an11 i d analog input 11 56 an12 i d analog input 12 55 an13 i d analog input 13 50 an14 i d analog input 14 49 an15 i d analog input 15 48 an16 i d analog input 16 47 an17 i d analog input 17 46 an18 i d analog input 18 table 4 pin definitions and functions (pg-lqfp-176-5 package 1) ) (cont?d) pin symbol ctrl. type function
tc1767 pinning data sheet 72 v1.4, 2012-07 45 an19 i d analog input 19 44 an20 i d analog input 20 43 an21 i d analog input 21 42 an22 i d analog input 22 41 an23 i d analog input 23 40 an24 i d analog input 24 39 an25 i d analog input 25 38 an26 i d analog input 26 37 an27 i d analog input 27 35 an28 i d analog input 28 34 an29 i d analog input 29 33 an30 i d analog input 30 32 an31 i d analog input 31 31 an32 i d analog input 32 30 an33 i d analog input 33 29 an34 i d analog input 34 28 an35 i d analog input 35 54 v ddm -- adc analog part power supply (3.3v - 5v) 53 v ssm -- adc analog part ground 52, v aref0 -- adc0 reference voltage v aref1 -- adc1 reference voltage 51 v agnd0 -- adc reference ground 24 v ddmf -- fadc analog part po wer supply (3.3v) 2) 23 v ddaf -- fadc analog part logic power supply (1.5v) 25, v ssmf -- fadc analog part ground v ssaf -- fadc analog part ground 26 v faref -- fadc reference voltage 27 v fagnd -- fadc reference ground table 4 pin definitions and functions (pg-lqfp-176-5 package 1) ) (cont?d) pin symbol ctrl. type function
tc1767 pinning data sheet 73 v1.4, 2012-07 10, 21 3) , 68, 84, 89, 99, 123, 153, 170 v dd -- digital core power supply (1.5v) 11, 20, 69, 83, 91, 100, 124, 139, 154, 171 v ddp -- port power supply (3.3v) 12, 22, 70, 82, 85, 92, 101, 125, 140, 155, 172 v ss -- digital ground 105 v ddosc -- main oscillator and pll power supply (1.5v) 106 v ddosc3 -- main oscillator power supply (3.3v) 104 v ssosc -- main oscillator and pll ground 141 v ddfl3 -- power supply for flash (3.3v) 102 xtal1 i main oscillator input 103 xtal2 o main oscillator output table 4 pin definitions and functions (pg-lqfp-176-5 package 1) ) (cont?d) pin symbol ctrl. type function
tc1767 pinning data sheet 74 v1.4, 2012-07 legend for table 4 column ? ctrl. ?: i = input (for gpio port lines with iocr bit field selection pcx = 0xxx b ) o = output o0 = output with iocr bit field selection pcx = 1x00 b o1 = output with iocr bit field selection pcx = 1x01 b (alt1) 111 tdi i a2/ pu jtag serial data input brkin i ocds break input line brkout o ocds break output line 112 tms i a2/ pd jtag state machine control input dap1 i/o device access port line 1 113 tdo i/o a2/ pu jtag serial data output dap2 i/o device access port line 2 brkin i ocds break input line brkout o ocds break output line 114 trst ia1/ pd jtag reset input 115 tck i a1/ pd jtag clock input dap0 i device access port line 0 118 testmode ipu test mode select input 120 esr1 i/o a2/ pd external system request reset input 1 121 porst ipd power on reset input (input pad with input spike-filter) 122 esr0 i/o a2 external system request reset input 0 default configuration during and after reset is open-drain driver, corresponding to a2 strong driver, sharp edge. the driver drives low during power-on reset. 1) tc1767 ed: pg-lqfp-176-6 2) this pin is also connected to the analog pow er supply for comparator of the adc module. 3) for the tc1767 emulation device (ed), this pin is bonded to vdd sb (ed stand by ram supply). in the tc1767 non ed device, this pin is bonded to a vdd pad. table 4 pin definitions and functions (pg-lqfp-176-5 package 1) ) (cont?d) pin symbol ctrl. type function
tc1767 pinning data sheet 75 v1.4, 2012-07 o2 = output with iocr bit field selection pcx = 1x10 b (alt2) o3 = output with iocr bit field selection pcx = 1x11(alt3) column ? type ?: a1 = pad class a1 (lvttl) a2 = pad class a2 (lvttl) f = pad class f (lvds/cmos) d = pad class d (adc) pu = with pull-up device connected during reset (porst = 0) pd = with pull-down device connected during reset (porst = 0) tr = tri-state during reset (porst = 0) 3.1.2 reset behavior of the pins table 5 describes the pull-up/pull-down behavior of the system i/o pins during power- on reset. table 5 list of pull-up/pull-down porst reset behavior of the pins pins porst =0 porst =1 all gpios, tdi, testmode pull-up porst , trst , tck, tms pull-down esr0 the open-drain driver is used to drive low. 1) 1) valid additionally after deactivation of porst until the internal reset phase has finished. see the scu chapter for details. pull-up 2) 2) see the scu_iocr register description. esr1 pull-down 3) 3) see the scu_iocr register description. tdo pull-up high-impedance
tc1767 identification registers data sheet 76 v1.4, 2012-07 4 identification registers the identification registers uniquely id entify a module or the whole device. table 6 tc1767 identification registers short name value address stepping adc0_id 0058 c000 h f010 1008 h ? adc1_id 0058 c000 h f010 1408 h ? asc0_id 0000 4402 h f000 0a08 h ? asc1_id 0000 4402 h f000 0b08 h ? can_id 002b c061 h f000 4008 h ? cbs_jdpid 0000 6350 h f000 0408 h ? cbs_jtagid 1015 9083 h f000 0464 h ? cps_id 0015 c007 h f7e0 ff08 h ? cpu_id 000a c006 h f7e1 fe18 h ? dma_id 001a c004 h f000 3c08 h ? dmi_id 0008 c005 h f87f fc08 h ? fadc_id 0027 c003 h f010 0408 h ? flash0_id 0053 c001 h f800 2008 h ? fpu_id 0054 c003 h f7e1 a020 h ? gpta0_id 0029 c005 h f000 1808 h ? lbcu_id 000f c005 h f87f fe08 h ? lfi_id 000c c006 h f87f ff08 h ? ltca2_id 002a c005 h f000 2808 h ? mchk_id 001b c001 h f010 c208 h ? mli0_id 0025 c007 h f010 c008 h ? msc0_id 0028 c003 h f000 0808 h ? pcp_id 0020 c006 h f004 3f08 h ? pmi_id 000b c005 h f87f fd08 h ? pmu0_id 0050 c001 h f800 0508 h ? sbcu_id 0000 6a0c h f000 0108 h ? scu_chipid 0000 9001 h f000 0640 h ? scu_id 0052 c001 h f000 0508 h ?
tc1767 identification registers data sheet 77 v1.4, 2012-07 scu_manid 0000 1820 h f000 0644 h ? scu_rtid 0000 0007 h f000 0648 h ad-step ssc0_id 0000 4511 h f010 0108 h ? ssc1_id 0000 4511 h f010 0208 h ? stm_id 0000 c006 h f000 0208 h ? table 6 tc1767 identification registers (cont?d) short name value address stepping
tc1767 electrical parameters data sheet 78 v1.4, 2012-07 5 electrical parameters 5.1 general parameters 5.1.1 parameter interpretation the parameters listed in this section partly represent the characteristics of the tc1767 and partly its requirements on the system. to aid interpreting the parameters easily when evaluating them for a design, they are marked with an two-letter abbreviation in column ?symbol?: ? cc such parameters indicate c ontroller c haracteristics which are a distinctive feature of the tc1767 and must be regarded for a system design. ? sr such parameters indicate s ystem r equirements which must provided by the microcontroller system in which the tc1767 designed in.
tc1767 electrical parameters data sheet 79 v1.4, 2012-07 5.1.2 pad driver and pad classes summary this section gives an overview on the different pad driver classes and its basic characteristics. more details (mainly dc parameters) are defined in the section 5.2.1 . table 7 pad driver and pad classes overview class power supply type sub class speed grade load leakage 1) 1) values are for t jmax =150c. termination a 3.3 v lvttl i/o, lvttl outputs a1 (e.g. gpio) 6 mhz 100 pf 500 na no a2 (e.g. serial i/os) 40 mhz 50 pf 6 aseries termination recommended f 3.3 v lvds/ cmos ?50 mhz ?? parallel termination 2) , 100 10% 2) in applications where the lvds pins are not used (d isabled), these pins must be either left unconnected, or properly terminated with the differential parallel termination of 100 10%. d e 5 v adc ? ? ? ? see table 12
tc1767 electrical parameters data sheet 80 v1.4, 2012-07 5.1.3 absolute maximum ratings stresses above those listed under ?absol ute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other condition s above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. during absolute maximum rating overload conditions ( v in > related v dd or v in < v ss ) the voltage on the related v dd pins with respect to ground ( v ss ) must not exceed the values defined by the absolute maximum ratings. table 8 absolute maximu m rating parameters parameter symbol values unit note / test con dition min. typ. max. ambient temperature t a sr -40 ? 125 c under bias storage temperature t st sr -65 ? 150 c? junction temperature t j sr -40 ? 150 c under bias voltage at 1.5 v power supply pins with respect to v ss 1) 1) applicable for v dd , v ddosc , v ddpll , and v ddaf . v dd sr ??2.25 v? voltage at 3.3 v power supply pins with respect to v ss 2) 2) applicable for v ddp , v ddfl3, and v ddmf . v ddp sr ? ? 3.75 v ? voltage at 5 v power supply pins with respect to v ss v ddm sr ? ? 5.5 v ? voltage on any class a input pin and dedicated input pins with respect to v ss v in sr -0.5 ? v ddp + 0.5 or max. 3.7 v whatever is lower voltage on any class d analog input pin with respect to v agnd v ain v arefx sr -0.5 ? v ddm + 0.5 v ? voltage on any class d analog input pin with respect to v ssaf , if the fadc is switched through to the pin. v ainf v faref sr -0.5 ? v ddm + 0.5 v ?
tc1767 electrical parameters data sheet 81 v1.4, 2012-07 5.1.4 operating conditions the following operating conditions must not be exceeded in order to ensure correct operation of the tc1767. all parameters specified in the following table refer to these operating conditions, unless otherwise noted. table 9 operating condition parameters parameter symbol values unit note / test condition min. typ. max. digital supply voltage 1) v dd sr v ddosc sr 1.42 ? 1.58 2) v? v ddp sr v ddosc3 sr 3.13 ? 3.47 3) v for class a pins (3.3 v 5%) v ddfl3 sr 3.13 ? 3.47 3) v? analog supply voltages v ddmf sr 3.13 ? 3.47 3) vfadc v ddaf sr 1.42 ? 1.58 2) vfadc v ddm sr 4.75 ? 5.25 v for class d e pins, adc digital ground voltage v ss sr 0 ? ? v ? ambient temperature under bias t a sr ? -40 125 c? analog supply voltages ? ? ? ? ? see separate specification page 88 , page 93 overload current at class d pins i ov -1 ? 3 ma 4) sum of overload current at class d pins | i ov | ? ? 10 ma per single adc overload coupling factor for analog inputs 5) k ovap ??5 10 -5 0 < i ov < 3 ma k ovan ??5 10 -4 -1 ma < i ov < 0 cpu & lmb bus frequency f cpu sr ? ? 133 80 mhz derivative dependent pcp frequency f pcp sr ? ? 133 80 mhz 6) derivative dependent fpi bus frequency f sys sr ? ? 80 mhz 6) short circuit current i sc sr -5 ? +5 ma 7)
tc1767 electrical parameters data sheet 82 v1.4, 2012-07 absolute sum of short circuit currents of a pin group (see table 10 ) | i sc_pg | sr ? ? 20 ma see note inactive device pin current i id sr -1 ? 1 ma all power supply voltages v ddx =0 absolute sum of short circuit currents of the device | i sc_d | sr ? ? 100 ma see note 4) external load capacitance c l sr ? ? ? pf depending on pin class. see dc characteristics 1) digital supply voltages applied to the tc1767 must be static regulated voltages which allow a typical voltage swing of 5%. 2) voltage overshoot up to 1.7 v is permissible at power-up and porst low, provided the pulse duration is less than 100 s and the cumulated summary of the pulses does not exceed 1 h. 3) voltage overshoot up to 4 v is permissible at power-up and porst low, provided the pulse duration is less than 100 s and the cumulated summary of the pulses does not exceed 1 h. 4) see additional document ?tc1767 pin reliability in over load? for definition of overload current on digital pins. 5) the overload coupling factor (ka) defines the worst case relation of an overload condition (iov) at one pin to the resulting leakage current (ileaktot) into an adjacent pin: ileaktot = ka |iov| + ioz1. thus under overload conditions an additional erro r leakage voltage (vael) will be induced onto an adjacent analog input pin due to the resistance of the anal og input source (rain). that means vael = rain |ileaktot|. the definition of adjacent pins is re lated to their order on the silicon. the injected leakage current always flows in the oppo site direction from the causing overload current. therefore, the total leakage current must be calculat ed as an algebraic sum of the both component leakage currents (the own leakage current ioz1 and the optional injected leakage current). 6) the pll jitter characteristics add to this value according to the application settings. see the pll jitter parameters. 7) applicable for digital outputs. table 10 pin groups for overload/short-circuit current sum parameter group pins 1 p5.[14:8] 2 p1.[14:12]; p2.[7:0] 3 p4.[3:0] 4 p1.[3:2]; p1.[11:8] table 9 operating condition parameters parameter symbol values unit note / test condition min. typ. max.
tc1767 electrical parameters data sheet 83 v1.4, 2012-07 5 p1.[7:4]; tdi/brkin /brkout ; trst , tck/dap0; p1.[ 1:0]; p1.15; testmode ; esr0 ; porst ; esr1 6 p3.[10:0]; p3.[15:14] 7 p3.[13:11]; p0.[3 :0]; p0.[11:8] 8 p6.[3:0]; p2.[13:8]; p0.[5:4]; p0.[13:12] 9 p0.[7:6]; p0.[15:14]; p5.[7:0]; p5.15 table 10 pin groups for overload/short-circuit current sum parameter group pins
tc1767 electrical parameters data sheet 84 v1.4, 2012-07 5.2 dc parameters 5.2.1 input/output pins table 11 input/output dc-characteristics (operating conditions apply) parameter symbol values unit note / test condition min. typ. max. general parameters pull-up current 1) | i puh | cc 10 ? 100 a v in < v ihamin ; class a1/a2/f/input pads. pull-down current 1) | i pdl | cc 10 ? 150 a v in > v ilamax ; class a1/a2/f/input pads. pin capacitance 1) (digital i/o) c io cc ??10pf f = 1 mhz t a = 25 c input only pads ( v ddp = 3.13 to 3.47 v = 3.3 v 5%) input low voltage v ili sr -0.3 ? 0.36 v ddp v? input high voltage v ihi sr 0.62 v ddp ? v ddp + 0.3 or max. 3.6 v whatever is lower ratio v il / v ih cc 0.58 ? ? ? ? input high voltage trst , tck v ihj sr 0.64 v ddp ? v ddp + 0.3 or max. 3.6 v whatever is lower input hysteresis hysi cc 0.1 v ddp ?? v 4) input leakage current 2) i ozi cc ?? 3000 6000 na (( v ddp /2)-1) < v in < (( v ddp /2)+1) otherwise spike filter always blocked pulse duration t sf1 cc ??10ns
tc1767 electrical parameters data sheet 85 v1.4, 2012-07 spike filter pass- through pulse duration t sf2 cc 100 ? ? ns class a pads ( v ddp = 3.13 to 3.47 v = 3.3v 5%) output low voltage 2)3) v ola cc ??0.4v i ol = 2 ma for medium and strong driver mode, i ol =500 a for weak driver mode output high voltage 2) 3) v oha cc 2.4 ? ? v i oh = -2 ma for medium and strong driver mode, i oh =-500 a for weak driver mode v ddp - 0.4 ?? v i oh = -1.4 ma for medium and strong driver mode, i oh =-400 a for weak driver mode input low voltage class a1/2 pins v ila sr -0.3 ? 0.36 v ddp v? input high voltage class a1 pins v iha1 sr 0.62 v ddp ? v ddp + 0.3 or max. 3.6 v whatever is lower ratio v il / v ih sr 0.58 ? ? ? ? input high voltage class a2 pins v iha2 sr 0.60 v ddp ? v ddp + 0.3 or max. 3.6 v whatever is lower ratio v il / v ih cc 0.60 ? ? ? ? input hysteresis hysa cc 0.1 v ddp ?? v 4) input leakage current class a2 pins i oza2 ?? 3000 6000 na (( v ddp /2)-1) < v in < (( v ddp /2)+1) otherwise 2) table 11 input/output dc-characteristics (cont?d)(operating conditions apply) parameter symbol values unit note / test condition min. typ. max.
tc1767 electrical parameters data sheet 86 v1.4, 2012-07 input leakage current class a1 pins i oza1 cc ?? 500 na 0 v < v in < v ddp class f pads, lvds mode ( v ddp = 3.13 to 3.47 v = 3.3v 5%) output low voltage v ol cc 875 ? mv parallel termination 100 1% output high voltage v oh cc ? 1525 mv parallel termination 100 1% output differential voltage v od cc 150 ? 400 mv parallel termination 100 1% output offset voltage v os cc 1075 ? 1325 mv parallel termination 100 1% output impedance r 0 cc 40 ? 140 ? class f pads, cmos mode ( v ddp = 3.13 to 3.47 v = 3.3v 5%) input low voltage class f pins v ilf sr -0.3 ? 0.36 v ddp v? input high voltage class f pins v ihf sr 0.6 v ddp ? v ddp + 0.3 or max 3.6 v whatever is lower input hysteresis class f pins hysf cc 0.05 v ddp ?? v input leakage current class f pins i ozf cc ?? 3000 6000 na (( v ddp /2)-1) < v in < (( v ddp /2)+1) otherwise 2) output low voltage 5) v olf cc ??0.4v i ol =2ma output high voltage 2) 5) v ohf cc 2.4 ? ? v i oh =-2ma v ddp - 0.4 ?? v i oh =-1.4ma class d pads see adc characteristics ? ? ? ? ? 1) not subject to production test, verified by design / characterization. 2) only one of these parameters is tested, the other is verified by design characterization table 11 input/output dc-characteristics (cont?d)(operating conditions apply) parameter symbol values unit note / test condition min. typ. max.
tc1767 electrical parameters data sheet 87 v1.4, 2012-07 3) maximum resistance of the driver r dson , defined for p_mos / n_mos transistor separately: 25 / 20 for strong driver mode, i oh / l <2ma, 200 / 150 for medium driver mode, i oh / l < 400 ua, 600 / 400 for weak driver mode, i oh / l < 100 ua, verified by design / characterization. 4) function verified by design, value verified by design characterization. hysteresis is implemented to avoid metastable st ates and switching due to internal ground bounce. it cannot be guaranteed that it suppresses switching due to external system noise. 5) the following constraint applies to an lvds pair used in cmos mode: only one pin of a pair should be used as output, the other should be used as input, or both pins should be used as inputs. using both pins as outputs is not recommended because of the higher crosstalk between them.
tc1767 electrical parameters data sheet 88 v1.4, 2012-07 5.2.2 analog to digital converters (adc0/adc1) all adc parameters are optimized for and valid in the range of v ddm = 5v 5%. table 12 adc characteristics (operating conditions apply) parameter symbol values unit note / test condition min. typ. max. analog supply voltage v ddm sr 4.75 5 5.25 v ? 3.13 3.3 3.47 1) v? v dd sr 1.42 1.5 1.58 2) v power supply for adc digital part, internal supply analog ground voltage v ssm sr -0.1 ? 0.1 v ? analog reference voltage 14) v arefx sr v agndx +1 v v ddm v ddm + 0.05 1)3)4) v? analog reference ground 14) v agndx sr v ssmx - 0.05v 0 v aref - 1v v? analog input voltage range v ain sr v agndx ? v arefx v? analog reference voltage range 5)14) v arefx - v agndx sr v ddm /2 ? v ddm + 0.05 v? converter clock f adc sr 1 ? 80 mhz ? internal adc clocks f adci cc 0.5 ? 10 mhz ? sample time t s cc 2 ? 257 t adci ? total unadjusted error 5) tue 6) cc ? ? 4 lsb 12-bit conversion, without noise 7)8) ?? 2 lsb 10-bit conversion 8) ?? 1 lsb 8-bit conversion 8) dnl error 9) 5) ea dnl cc ? 1.5 3.0 lsb 12-bit conversion without noise 8)10) inl error 9)5) ea inl cc ? 1.5 3.0 lsb 12-bit conversion without noise 8)10) gain error 9)5) ea gain cc ? 0.5 3.5 lsb 12-bit conversion without noise 8)10)
tc1767 electrical parameters data sheet 89 v1.4, 2012-07 offset error 9)5) ea off cc ? 1.0 4.0 lsb 12-bit conversion without noise 8)10) input leakage current at analog inputs of adc0/1 11) 12) 13) i oz1 cc -300 ? 100 na (0% v ddm ) < v in < (3% v ddm ) -100 ? 200 na (3% v ddm ) < v in < (97% v ddm ) -100 ? 300 na (97% v ddm ) < v in < (100% v ddm ) input leakage current at v aref0/1 , per module i oz2 cc ? ? 1.5 a0v< v aref < v ddm, no conversion running input current at v aref0/1 14) , per module i aref cc ? 35 75 a rms 0v< v aref < v ddm 15) total capacitance of the voltage reference inputs 16)14) c areftot cc ?2040pf 8) switched capacitance at the positive reference voltage input 14) c arefsw cc ?1530pf 8)17) resistance of the reference voltage input path 16) r aref cc ? 500 1000 500 ohm increased for an[1:0] used as reference input 8) total capacitance of the analog inputs 16) c aintot cc ?2530pf 1)8) table 12 adc characteristics (cont?d) (operating conditions apply) parameter symbol values unit note / test condition min. typ. max.
tc1767 electrical parameters data sheet 90 v1.4, 2012-07 switched capacitance at the analog voltage inputs c ainsw cc ? 7 20 pf 8)18) on resistance of the transmission gates in the analog voltage path r ain cc ? 700 1500 8) on resistance for the adc test (pull-down for ain7) r ain7t cc 180 550 900 19) test feature available only for ain7 8) 20) current through resistance for the adc test (pull- down for ain7) i ain7t cc ? 15 rms 30 peak ma test feature available only for ain7 8) 1) voltage overshoot up to 4 v is permissible at power-up and porst low, provided the pulse duration is less than 100 s and the cumulated summary of the pulses does not exceed 1 h. 2) voltage overshoot up to 1.7 v is permissible at power-up and porst low, provided the pulse duration is less than 100 s and the cumulated summary of the pulses does not exceed 1 h. 3) a running conversion may become inexact in case of violating the normal operating conditions (voltage overshoot). 4) if the reference voltage v aref increases or the v ddm decreases, so that v aref =( v ddm + 0.05 v to v ddm + 0.07 v), then the accuracy of the adc decreases by 4 lsb12. 5) if a reduced reference voltage in a range of v ddm /2 to v ddm is used, then the adc converter errors increase. if the reference voltage is reduced with the factor k (k<1), then tue, dnl, inl gain and offset errors increase with the factor 1/k. if a reduced reference voltage in a range of 1 v to v ddm /2 is used, then there are additional decrease in the adc speed and accuracy. 6) tue is tested at v aref =5.0v, v agnd = 0 v and v ddm =5.0v 7) adc module capability. 8) not subject to production test, verified by design / characterization. 9) the sum of dnl/inl/gain/offset errors does not exceed the related tue total unadjusted error. 10) for 10-bit conversions the dnl/inl/gain/offset error values must be multiplied with factor 0.25. for 8-bit conversions the dnl/inl/gain/offset error values must be multiplied with 0.0625. 11) the leakage current definition is a continuous function, as shown in figure 19 . the numerical values defined determine the characteristic points of the given cont inuous linear approximation - they do not define step function. table 12 adc characteristics (cont?d) (operating conditions apply) parameter symbol values unit note / test condition min. typ. max.
tc1767 electrical parameters data sheet 91 v1.4, 2012-07 figure 17 adc0/adc1 clock circuit 12) only one of these parameters is tested, the other is verified by design characterization. 13) the leakage current decreases typically 30% for junction temperature decrease of 10 o c. 14) applies to ainx, when used as auxiliary reference inputs. 15) i aref_max is valid for the minimum specified conversion time. the current flowing during an adc conversion with a duration of up to t c = 25s can be calculated with the formula i aref_max = q conv / t c . every conversion needs a total charge of q conv = 150pc from v aref . all adc conversions with a duration longer than t c = 25s consume an i aref_max = 6a. 16) for the definition of the parameters see also figure 18 . 17) this represents an equivalent switched capacitance. this capacitance is not switched to the reference voltage at once. instead of this smalle r capacitances are successively switched to the reference voltage. 18) the sampling capacity of the conversion c-network is pre-charged to v aref /2 before the sampling moment. because of the parasitic elements the volt age measured at ainx can deviate from v aref /2, and is typically 1.35v. 19) r ain7t = 1400 ohm maximum and 830 ohm typical in the v ddm =3.3v 5% range. 20) the dc current at the pin is limited to 3 ma for the operational lifetime. adc_clocking analog part analog clock f adci digital clock f adcd f adc arbiter divider for f adcd registers interrupts, etc. clock generation divider for f adci adc kernel
tc1767 electrical parameters data sheet 92 v1.4, 2012-07 figure 18 adc0/adc1 input circuits figure 19 adc0/adc1analog inputs leakage table 13 conversion time (operating conditions apply) parameter symbol value unit note conversion time with post-calibration t c cc 2 t adc +(4+stc+n) t adci s n = 8, 10, 12 for n - bit conversion t adc =1/ f adc t adci =1/ f adci conversion time without post-calibration 2 t adc +(2+stc+n) t adci reference voltage input circuitry analog input circuitry analog_inprefdiag r ext = v ain c ext r ain, on c aintot - c ainsw c ainsw anx v aref r aref, on c areftot - c arefsw c arefsw v agndx v arefx r ain7t v agndx v in [v ddm %] 200na 300na 3% 100% 97% ioz1 -300na -100na adc leakage 10.vsd 100na
tc1767 electrical parameters data sheet 93 v1.4, 2012-07 5.2.3 fast analog to digital converter (fadc) all parameters apply to fadc used in diffe rential mode, which is the default and the intended mode of operation, and which ta kes advantage of many error cancelation effects inherent to differential measurements in general. table 14 fadc characteristics (operating conditions apply) parameter symbol values unit note / test condition min. typ. max. dnl error ef dnl cc ? ? 1 lsb 9) inl error ef inl cc ? ? 4 lsb 9) gradient error 9) ef grad cc ? ? 5 % without calibration gain 1, 2, 4 ? ? 6 % without calibration gain 8 offset error 9)1) ef off 2) cc ??20 3) mv with calibration 1) ??90 3) mv without calibration reference error of internal v faref /2 ef ref cc ??60mv? analog supply voltages v ddmf sr 3.13 ? 3.47 4) v? v ddaf sr 1.42 ? 1.58 5) v? analog ground voltage v ssaf sr -0.1 ? 0.1 v ? analog reference voltage v faref sr 3.13 ? 3.47 4)6) v nominal 3.3 v analog reference ground v fagnd sr v ssaf - 0.05 v ? v ssaf + 0.05 v v? analog input voltage range v ainf sr v fagnd ? v ddmf v? analog supply currents i ddmf sr ? ? 10 ma ? i ddaf sr ? ? 10 ma 7) input current at v faref i faref cc ??120 a rms independent of conversion input leakage current at v faref 8) i foz2 cc ? ? 500 na 0 v < v in < v ddmf input leakage current at v fagnd 8) i foz3 cc ??8 a0v< v in < v ddmf
tc1767 electrical parameters data sheet 94 v1.4, 2012-07 the calibration procedure should run after each power-up, when all power supply voltages and the referenc e voltage have stabilized. conversion time t c_fadc cc ? ? 21 clk of f fadc for 10-bit conv. converter clock f fadc sr 10 ? 80 mhz ? input resistance of the analog voltage path (rn, rp) r fain cc 100 ? 200 k 9) channel amplifier cutoff frequency 9) f coff cc 2?? mhz? settling time of a channel amplifier (after changing channel amplifier input) 9) t set cc ? ? 5 s? 1) calibration should be performed at each power-up. in case of continuous operation, calibration should be performed minimum once per week, or on regular basis in order to compensate for temperature changes. 2) the offset error voltage drifts over th e whole temperature range maximum 6 lsb. 3) applies when the gain of the channel equals one. for the other gain settings, the offset error increases; it must be multiplied with the applied gain. 4) voltage overshoots up to 4 v are permissible , provided the pulse duration is less than 100 s and the cumulated summary of the pulses does not exceed 1 h. 5) voltage overshoots up to 1.7 v are permissible, provided the pulse duration is less than 100 s and the cumulated sum of the pulses does not exceed 1 h. 6) a running conversion may become inexact in case of violating the normal operating conditions (voltage overshoots). 7) current peaks of up to 40 ma with a duration of max. 2 ns may occur 8) this value applies in power-down mode. 9) not subject to production test, verified by design / characterization. table 14 fadc characteristics (operating conditions apply) (cont?d) parameter symbol values unit note / test condition min. typ. max.
tc1767 electrical parameters data sheet 95 v1.4, 2012-07 figure 20 fadc input circuits fadc_inprefdi ag = + - + - r n fainxn fainxp v fa g nd fadc analog input stage r p v faref /2 v faref fadc reference voltage input circuitry v fag nd v faref i faref
tc1767 electrical parameters data sheet 96 v1.4, 2012-07 5.2.4 oscillator pins note: it is strongly recomm ended to measure the oscill ation allowance (negative resistance) in the final target system (layout) to determine th e optimal parameters for the oscillator operation. refer to t he limits specified by the crystal supplier. 5.2.5 temperature sensor table 15 oscillator pins characteristics (operating conditions apply) parameter symbol values unit note / test condition min. typ. max. frequency range f osc cc 8 ? 25 mhz external crystal mode selected input low voltage at xtal1 1) 1) if the xtal1 pin is driven by a crystal, reac hing a minimum amplitude (peak-to-peak) of 0.3 v ddosc3 is sufficient. v ilx sr -0.2 ? 0.3 v ddosc3 v? input high voltage at xtal1 1) v ihx sr 0.7 v ddosc3 ? v ddosc3 + 0.2 v? input current at xtal1 i ix1 cc ? ? 25 a0 v < v in < v ddosc3 table 16 temperature sensor characteristics (operating conditions apply) parameter symbol values unit note / test condition min. typ. max. temperature sensor range t sr sr -40 150 c junction temperature temperature sensor measurement time t tsmt sr ? ? 100 s? start-up time after reset t tsst sr ? ? 10 s? sensor accuracy 1) 1) dts specs limit of 6 o c is guaranteed by design/characterizati on. not subjected to production test. t tsa cc ? ? 6ccalibrated
tc1767 electrical parameters data sheet 97 v1.4, 2012-07 the following formula calculates the temperature measured by the dts in [ o c] from the result bitfield of the dtsstat register. (1) tj dtsstat result 619 ? 228 , ----------------------------------------------------------------- - =
tc1767 electrical parameters data sheet 98 v1.4, 2012-07 5.2.6 power supply current the default test conditions (differe nces explicitly specified) are: v dd =1.58v, v ddp =3.47v, t j =150 o c. all other operating conditions apply. table 17 power supply currents, maximum power consumption parameter symbol values unit note / test condition min. typ. max. core active mode supply current 1) 2) 1) infineon power loop: cpu and pcp running, all peripher als active. the power consumption of each custom application will most probably be lower than this value, but must be evaluated separately.. 2) the i dd maximum value is 275 ma at f cpu = 80 mhz, constant t j =150 o c, for the infineon max power loop. the dependency in this range is, at c onstant junction temperature, linear. f cpu / f sys = 1:1 mode. i dd cc ? ? 330 ma f cpu =133 mhz f cpu / f sys =2:1 realistic core active mode supply current 3)4) ??230ma v dd =1.53v, t j =150 o c fadc 3.3 v analog supply current i ddmf cc ? ? 10 ma ? fadc 1.5 v analog supply current i ddaf cc ? ? 10 ma ? 4) flash memory 3.3 v supply current i ddfl3r cc ? ? 60 ma continuously reading the flash memory 5) i ddfl3e cc ? ? 61 ma flash memory erase-verify 6) oscillator 1.5 v supply i ddosc cc ? ? 3 ma ? 4) oscillator 3.3 v supply i ddosc3 cc ? ? 10 ma ? 4) lvds 3.3 v supply i lvds ? ? 15 ma in total for two pairs pad currents,sum of v ddp 3.3 v supplies i ddp cc ? ? 16 ma ? 4) 7) i ddp_fp cc ? ? 34 ma i ddp including data flash programming current 4) 8) adc 5 v power supply i ddm cc ? 2 3 ma adc0 / 1 maximum average power dissipation 1) p d sr ? 820 990 mw worst case t a =125 o c, p d r ja < 25 o c
tc1767 electrical parameters data sheet 99 v1.4, 2012-07 3) the i dd maximum value is 180 ma at f cpu = 80 mhz, constant t j =150 o c, for the realistic pattern. the dependency in this range is, at c onstant junction temperature, linear. f cpu / f sys = 1:1 mode. 4) not tested in production separately, verified by design / characterization. 5) this value assumes worst case of reading flash line with all cells erased. in case of 50% cells written with ?1? and 50% cells written with ?0?, the maximum current drops down to 53 ma. 6) relevant for the power supply dimensi oning, not for thermal considerations. in case of erase of data flash, internal flash array loading effects may generate transient current spikes of up to 15 ma for maximum 5 ms. 7) no gpio activity, lvds off 8) this value is relevant for the power suppl y dimensioning not for thermal considerations. the currents caused by the gpio activity depend on the particular application and should be added separately.
tc1767 electrical parameters data sheet 100 v1.4, 2012-07 5.3 ac parameters all ac parameters are defined with the te mperature compensation disabled. that means, keeping the pads constantly at maximum strength. 5.3.1 testing waveforms figure 21 rise/fall time parameters figure 22 testing waveform, output delay figure 23 testing waveform, output high impedance 10 % 90 % 10 % 90 % v ss v ddp t r rise_fall_vddp.vsd t f mct04881_vddp.vsd v ddp / 2 test points v ddp / 2 v ss v ddp mct04880_new v load + 0.1 v v oh - 0.1 v timing reference points v load - 0.1 v v ol - 0.1 v
tc1767 electrical parameters data sheet 101 v1.4, 2012-07 5.3.2 output rise/fall times table 18 output rise/fall times (operating conditions apply) parameter symbol values unit note / test condition min. typ. max. class a1 pads rise/fall times 1) 1) not all parameters are subject to production test, but ve rified by design/characterization and test correlation. t ra1 , t fa1 ??50 140 18000 150 550 65000 ns regular (medium) driver, 50 pf regular (medium) driver, 150 pf regular (medium) driver, 20 nf weak driver, 20 pf weak driver, 150 pf weak driver, 20 000 pf class a2 pads rise/fall times 1) t ra2 , t fa2 ??3.7 7.5 7 18 50 140 18000 150 550 65000 ns strong driver, sharp edge, 50 pf strong driver, sharp edge, 100pf strong driver, med. edge, 50 pf strong driver, soft edge, 50 pf medium driver, 50 pf medium driver, 150 pf medium driver, 20 000 pf weak driver, 20 pf weak driver, 150 pf weak driver, 20 000 pf class f pads rise/fall times t rf1 , t ff1 ? ? 2 ns lvds mode rise/fall times t rf2 , t ff2 ? ? 60 ns cmos mode, 50 pf
tc1767 electrical parameters data sheet 102 v1.4, 2012-07 5.3.3 power sequencing figure24 5v / 3.3v / 1.5v power-up/down sequence the following list of rules applies to the power-up/down sequence: ? all ground pins v ss must be externally connected to one single star point in the system. regarding the dc current component, all ground pins are internally directly connected. 1. at any moment, each power supply must be higher than any lower_power_supply - 0.5 v, or: v dd5 > v dd3.3 - 0.5 v; v dd5 > v dd1.5 - 0.5 v; v dd3.3 > v dd1.5 - 0.5 v, see figure 24 . 2. during power-up and power-down, the vo ltage difference between the power supply pins of the same voltage (3.3 v, 1.5 v, an d 5 v) with different names (for example v ddp , v ddfl3 ...), that are internaly connected via diodes must be lower than 100 mv. on the other hand, all power supply pi ns with the same name (for example all v ddp ), are internaly directly connected. it is recommended that the power pins of the same voltage are driven by a single power supply. power-up 8.vsd 1.5v 3.3v 5v t v +-5% +-5% +-5% t -12% -12% porst 0.5v 0.5v 0.5v v ddp v aref power down power fail
tc1767 electrical parameters data sheet 103 v1.4, 2012-07 3. the porst signal may be deactivated after all v dd5 , v dd3.3 , v dd1.5 , and v aref power- supplies and the oscillator have reac hed stable operation, within the normal operating conditions. 4. at normal power down the porst signal should be activated within the normal operating range, and then the power supp lies may be switched off. care must be taken that all flash write or dele te sequences have been completed. 5. at power fail the porst signal must be activated at latest when any 3.3 v or 1.5 v power supply voltage falls 12% below the nominal level. the same limit of 3.3 v-12% applies to the 5 v power supply too. i f, under these conditions, the porst is activated during a flash write, only the memory row that was the target of the write at the moment of the power loss will cont ain unreliable content. in order to ensure clean power-down behavior, the porst signal should be activated as close as possible to the normal operating voltage range. 6. in case of a power-loss at any power-supply, all power supplies must be powered- down, conforming at the same time to the rules number 2 and 4. 7. although not necessary, it is additionally recommended that all power supplies are powered-up/down together in a controlled way, as tight to each other as possible. 8. aditionally, regarding the adc reference voltage v aref : ? v aref must power-up at the same time or later than v ddm , and ? v aref must power-down eather earlier or at latest to satisfy the condition v aref < v ddm + 0.5 v. this is required in or der to prevent discharge of v aref filter capacitance through the esd diodes through the v ddm power supply. in case of discharging the reference capacitance through the esd diodes, the current must be lower than 5 ma.
tc1767 electrical parameters data sheet 104 v1.4, 2012-07 5.3.4 power, pad and reset timing table 19 power, pad and reset timing parameters parameter symbol values unit note / test conditi on min. typ. max. min. v ddp voltage to ensure defined pad states 1) 1) this parameter is valid under assumption that porst signal is constantly at low level during the power- up/power-down of the v ddp . v ddppa cc 0.6 ? ? v ? oscillator start-up time 2) t oscs cc ? ? 10 ms ? minimum porst active time after power supplies are stable at operating levels t poa sr 10 ? ? ms ? esr0 pulse width t hd cc program mable 3)5) ?? f sys ? porst rise time t por sr ? ? 50 ms ? setup time to porst rising edge 4) t pos sr 0 ? ? ns ? hold time from porst rising edge t poh sr 100 ? ? ns testmode trst setup time to esr0 rising edge t hds sr 0 ? ? ns ? hold time from esr0 rising edge t hdh sr 16 1/ f sys 5) ? ? ns hwcfg ports inactive after porst reset active 6)7) t pip cc ? ? 150 ns ? ports inactive after esr0 reset active (and for all logic) t pi cc ? ? 8 1/ f sys ns ? power on reset boot time 8) t bp cc ? ? 2.5 ms ? application reset boot time 9)10) t b cc 150 ? 700 s f cpu =133mhz 150 ? 960 s f cpu =80mhz
tc1767 electrical parameters data sheet 105 v1.4, 2012-07 figure 25 power, pad and reset timing 2) t oscs is defined from the moment when v ddosc3 = 3.13 v until the oscillations reach an amplitude at xtal1 of 0,3 v ddosc3 . this parameter is verified by device characterization. the extern al oscillator circuitry must be optimized by the customer and chec ked for negative resistance as recommended and specified by crystal suppliers. 3) any esr0 activation is internally prolonged to scu_rstcntcon.relsa fpi bus clock ( f fpi ) cycles. 4) applicable for input pins testmode and trst . 5) f fpi = f cpu /2 6) not subject to production test, verified by design / characterization. 7) this parameter includes the delay of the analog spike filter in the porst pad. 8) the duration of the boot-time is defined between the rising edge of the porst and the moment when the first user instruction has entered the cpu and its processing starts. 9) the duration of the boot time is defined between the ri sing edge of the internal application reset and the clock cycle when the first user instruction has entered the cpu pipeline and its processing starts. 10) the given time includes the time of the internal reset extension for a configured value of scu_rstcntcon.relsa = 0x05be. reset_beh2 as programmed vddp pads pad- state undefined vdd v ddppa v ddppa t hd t poa t poa trst testmode esr0 porst t poh hwcfg t hdh t pip t pi tri -state or pull device active t hd t poh t hdh t pip t pi t pip t pi t pi t hdh t pi v ddp -12% v dd -12%
tc1767 electrical parameters data sheet 106 v1.4, 2012-07 5.3.5 phase locked loop (pll) note: all pll characteristics defined on this and the next page are not subject to production test, but verified by design characterization. phase locked loop operation when pll operation is enabled and configured, the pll clock f vco (and with it the lmb- bus clock f lmb ) is constantly adjusted to the sele cted frequency. the pll is constantly adjusting its output frequency to correspond to the input frequency (from crystal or clock source), resulting in an accumulated jitter t hat is limited. this means that the relative deviation for periods of more than one clock cycle is lower than for a single clock cycle. this is especially important for bus cycles using waitstates and for the operation of timers, serial interfaces, etc. for all slower operations and lo nger periods (e.g. pulse train generation or measurement, lower baudrates, et c.) the deviation caused by the pll jitter is negligible. two formulas are defined for the (absolute) approximate maximum value of jitter d m in [ns] dependent on the k2 - factor, the lmb clock frequency f lmb in [mhz], and the number m of consecutive f lmb clock periods. (2) (3) table 20 pll parameters (operating conditions apply) parameter symbol values unit note / test con dition min. typ. max. accumulated jitter |d m |? ?7 ns? vco frequency range f vco 400 ? 800 mhz ? vco input frequency range f ref 8?16mhz? pll base frequency 1) 1) the cpu base frequency with which the application software starts after porst is calculated by dividing the limit values by 16 (this is the k2 factor after reset). f pllbase 50 200 320 mhz ? pll lock-in time t l ? ? 200 s? for k2 100 () and m f lmb mhz [] () 2 ? () d mns [] 740 k2 f lmb mhz [] -------------------------------------------- - 5 + ?? ?? 1001 , k2 ? () m1 ? () 05 , f lmb mhz [] 1 ? ---------------------------------------------------------------- 001 , k2 + ?? ?? = else d mns [] 740 k2 f lmb mhz [] -------------------------------------------- - 5 + =
tc1767 electrical parameters data sheet 107 v1.4, 2012-07 with rising number m of clock cycles the maximum jitter increases linearly up to a value of m that is defined by the k2-factor of the pll. beyond this value of m the maximum accumulated jitter remains at a constant valu e. further, a lower lmb-bus clock frequency f lmb results in a higher abso lute maximum jitter value. figure 26 gives the jitter curves for several k2 / f lmb combinations. figure 26 approximated maximum accumulated pll jitter for typical lmb- bus clock frequencies f lmb note: the specified pll jitter values are va lid if the capacitive l oad per output pin does not exceed c l = 20 pf with the maximum driver and sharp edge. in case of applications with many pins with high loads, driver strengths and toggle rates the specified jitter values could be exceeded. note: the maximum peak-to-peak noise on the pad supply voltage, measured between v ddosc3 at pin 106 and v ssosc at pin 104, is limited to a peak-to-peak voltage of v pp = 100 mv for noise frequencies below 300 khz and v pp =40mv for noise frequencies above 300 khz. the maximum peak-to peak noise on the pad supply votage, measured between v ddosc at pin 105 and v ssosc at pin 104, is limited to a peak-to-peak voltage of v pp = 100 mv for noise frequencies below 300 khz and v pp =40mv for noise frequencies above 300 khz. 0 0.0 m ns dm 2.0 4.0 6.0 10.0 20 40 60 80 100 120 8.0 o tc1767_pll_jitt_c f lmb = 40 mhz ( k2 = 10) f lmb = 40 mhz ( k2 = 20) f lmb = 133 mhz ( k2 = 6) f lmb = 80 mhz ( k2 = 10) = max. jitter = number of consecutive f lmb periods = k2-divider of pll dm m k2 o 7.0 f lmb = 80 mhz ( k2 = 6) 1.0
tc1767 electrical parameters data sheet 108 v1.4, 2012-07 these conditions can be achieved by appr opriate blocking of the supply voltage as near as possible to the supply pins and using pcb supply and ground planes.
tc1767 electrical parameters data sheet 109 v1.4, 2012-07 5.3.6 jtag interface timing the following parameters are applicable for communication through the jtag debug interface. the jtag module is fu lly compliant with ieee1149.1-2000. note: these parameters are not subject to pr oduction test but verified by design and/or characterization. table 21 jtag interface timing parameters (operating conditions apply) parameter symbol values unit note / test condition min. typ. max. tck clock period t 1 sr 25 ? ? ns ? tck high time t 2 sr 12 ? ? ns ? tck low time t 3 sr 10 ? ? ns ? tck clock rise time t 4 sr??4ns? tck clock fall time t 5 sr??4ns? tdi/tms setup to tck rising edge t 6 sr6??ns? tdi/tms hold after tck rising edge t 7 sr6??ns? tdo valid after tck falling edge 1) (propagation delay) 1) the falling edge on tck is used to generate the tdo timing. t 8 cc ? ? 13 ns c l =50pf t 8 cc??3nsc l =20pf tdo hold after tck falling edge 1) t 18 cc2??ns tdo high imped. to valid from tck falling edge 1)2) 2) the setup time for tdo is given implicitly by the tck cycle time. t 9 cc ? ? 14 ns c l =50pf tdo valid to high imped. from tck falling edge 1) t 10 cc ? ? 13.5 ns c l =50pf
tc1767 electrical parameters data sheet 110 v1.4, 2012-07 figure 27 test clock timing (tck) figure 28 jtag timing mc_jtag_tck 0.9 v ddp 0.5 v ddp t 1 t 2 t 3 0.1 v ddp t 5 t 4 t 6 t 7 t 6 t 7 t 9 t 8 t 10 tck tms tdi tdo mc_jtag t 18
tc1767 electrical parameters data sheet 111 v1.4, 2012-07 5.3.7 dap interface timing the following parameters are applicable for communication through the dap debug interface. note: these parameters are not subject to pr oduction test but verified by design and/or characterization. figure 29 test clock timing (dap0) table 22 dap interfa ce timing parameters (operating conditions apply) parameter symbol values unit note / test condition min. typ. max. dap0 clock period t 11 sr 12.5 ? ? ns ? dap0 high time t 12 sr4??ns? dap0 low time t 13 sr4??ns? dap0 clock rise time t 14 sr??2ns? dap0 clock fall time t 15 sr??2ns? dap1 setup to dap0 rising edge t 16 sr6??ns? dap1 hold after dap0 rising edge t 17 sr6??ns? dap1 valid per dap0 clock period 1) 1) the host has to find a suitable sampling point by analyzing the sync telegram response. t 19 sr8??ns80 mhz, c l =20pf t 19 sr 10 ? ? ns 40 mhz, c l =50pf mc_dap0 0.9 v ddp 0.5 v ddp t 11 t 12 t 13 0.1 v ddp t 15 t 14
tc1767 electrical parameters data sheet 112 v1.4, 2012-07 figure 30 dap timing host to device figure 31 dap timing device to host t 16 t 17 dap0 dap1 mc_ dap1_rx dap1 mc_ dap1_tx t 11 t 19
tc1767 electrical parameters data sheet 113 v1.4, 2012-07 5.3.8 peripheral timings note: peripheral timing parameters are not su bject to production test. they are verified by design / characterization. 5.3.8.1 micro link interface (mli) timing figure 32 mli interface timing note: the generation of rreadyx is in the input clock domain of the receiver. the reception of treadyx is asynchronous to tclkx. t 27 t 25 t 26 t 16 t 17 t 15 t 15 mli_tmg_2.vsd tdatax tvalidx tclkx rdatax rvalidx rclkx treadyx rreadyx t 10 t 13 t 11 t 12 t 14 t 20 t 27 mli transmitter timing mli receiver timing t 23 t 21 t 22 t 24
tc1767 electrical parameters data sheet 114 v1.4, 2012-07 table 23 mli transmitter/receiver timing (operating conditions apply), c l = 50 pf parameter symbol values unit note / test co ndition min. typ. max. mli transmi tter timing tclk clock period t 10 cc 2 t mli ?? ns 1) 1) t mlimin. = t sys = 1/ f sys . when f sys = 80 mhz, t 10 = 25 ns and t 20 = 12.5 ns. tclk high time t 11 cc 0.45 t 10 0.5 t 10 0.55 t 10 ns 2)3) 2) the following formula is valid: t 11 + t 12 = t 10 3) the min./max. tclk low/high times t 11 /t 12 include the pll jitter of f sys . fractional divider settings must be regarded additionally to t 11 /t 12 . tclk low time t 12 cc 0.45 t 10 0.5 t 10 0.55 t 10 ns 2)3) tclk rise time t 13 cc ? ? 4) 4) for high-speed mli interface, strong driver sharp edg e selection (class a2 pad) is recommended for tclk. ns ? tclk fall time t 14 cc ? ? 4) ns ? tdata/tvalid output delay time t 15 cc -3 ? 4.4 ns ? tready setup time to tclk rising edge t 16 sr 18 ? ? ns ? tready hold time from tclk rising edge t 17 sr 0 ? ? ns ? mli receiver timing rclk clock period t 20 sr 1 t mli ?? ns 1) rclk high time t 21 sr ? 0.5 t 20 ?ns 5)6) 5) the following formula is valid: t 21 + t 22 = t 20 6) the min. and max. value of is parameter can be adju sted by considering the other receiver timing parameters. rclk low time t 22 sr ? 0.5 t 20 ?ns 5)6) rclk rise time t 23 sr ? ? 4 ns 7) rclk fall time t 24 sr ? ? 4 ns 7) rdata/rvalid setup time to rclk falling edge t 25 sr 4.2 ? ? ns ? rdata/rvalid hold time from rclk rising edge t 26 sr 2.2 ? ? ns ? rready output delay time t 27 cc 0 ? 16 ns ?
tc1767 electrical parameters data sheet 115 v1.4, 2012-07 5.3.8.2 micro second channel (msc) interface timing figure 33 msc interface timing note: sample the data at sop with the falling edge of fclp in the target device. 5.3.8.3 ssc master / slave mode timing 7) the rclk max. input rise/fall times are best case parameters for f sys = 80 mhz. for reduction of emi, slower input signal rise/fall times can be used for longer rclk clock periods. table 24 msc interface timing (operating conditions apply), c l = 50 pf parameter symbol values unit note / test con dition min. typ. max. fclp clock period 1)2) 1) fclp signal rise/fall times are the same as the a2 pads rise/fall times. 2) fclp signal high and low can be minimum 1 t msc . t 40 cc 2 t msc 3) 3) t mscmin = t sys = 1/ f sys . when f sys = 80 mhz, t 40 = 25 ns ?? ns? sop/enx outputs delay from fclp rising edge t 45 cc -10 10 ns ? sdi bit time t 46 cc 8 t msc ?ns? sdi rise time t 48 sr 100 ns ? sdi fall time t 49 sr 100 ns ? msc_tmg_1.vsd t 45 t 45 t 40 0.1 v ddp 0.9 v ddp t 46 t 48 0.1 v ddp 0.9 v ddp t 49 t 46 sop en fclp sdi
tc1767 electrical parameters data sheet 116 v1.4, 2012-07 table 25 ssc master/slave mode timing (operating conditions apply), c l = 50 pf parameter symbol values unit note / test con dition min. typ. max. master mode timing sclk clock period t 50 cc 2 t ssc ?? ns 1)2)3) 1) sclk signal rise/fall times are the same as the a2 pads rise/fall times. 2) sclk signal high and low times can be minimum 1 t ssc . 3) t sscmin = t sys = 1/ f sys . when f sys = 80 mhz, t 50 = 25 ns. mtsr/slsox delay from sclk rising edge t 51 cc 0 ? 8 ns ? mrst setup to sclk falling edge t 52 sr 13 ? ? ns 3) mrst hold from sclk falling edge t 53 sr 0 ? ? ns 3) slave mode timing sclk clock period t 54 sr 4 t ssc ?? ns 1)3) sclk duty cycle t 55 / t 54 sr 45 ? 55 % ? mtsr setup to sclk latching edge t 56 sr t ssc +5 ? ? ns 3)4) 4) fractional divider switched off, ssc internal baud rate generation used. mtsr hold from sclk latching edge t 57 sr t ssc +5 ? ? ns 3)4) slsi setup to first sclk latching edge t 58 sr t ssc +5 ? ? ns 3) slsi hold from last sclk latching edge t 59 sr 7 ? ? ns ? mrst delay from sclk shift edge t 60 cc 0 ? 15 ns ? slsi to valid data on mrst t 61 cc ? ? 10 ns ?
tc1767 electrical parameters data sheet 117 v1.4, 2012-07 figure 34 ssc master mode timing figure 35 ssc slave mode timing ssc_tmgmm sclk 1)2) mtsr 1) t 51 t 51 mrst 1) t 53 data valid t 52 slsox 2) t 51 1) this timing is based on the following setup: con.ph = con.po = 0. 2) the transition at slsox is based on the following setup: ssotc.trail = 0 and the first sclk high pulse is in the first one of a transmission. t 50 ssc_tmgsm sclk 1) t 55 mtsr 1) t 57 data valid t 56 slsi t 58 1) this timing is based on the following setup: con.ph = con.po = 0. t 54 t 55 t 59 last latching sclk edge first latching sclk edge t 57 data valid t 56 mrst 1) t 60 first shift sclk edge t 60 t 61
tc1767 electrical parameters data sheet 118 v1.4, 2012-07 5.4 package and reliability 5.4.1 package parameters table 26 thermal parameters (operating conditions apply) device package r jct 1) 1) the top and bottom thermal resistances between the case and the ambient ( r tcat , r tcab ) are to be combined with the thermal resistances between the junction and the case given above ( r tjct , r tjcb ), in order to calculate the total thermal resistance between the junction and the ambient ( r tja ). the thermal resistances between the case and the ambient ( r tcat , r tcab ) depend on the external system (pcb, case) characteristics, and are under user responsibility. the junction temperature can be calculated using the following equation: t j = t a + r tja p d , where the r tja is the total thermal resistance between the junction and the ambient. this total junction ambient resistance r tja can be obtained from the upper fo ur partial thermal resistances. thermal resistances as measured by the ?cold plate method? (mil spec-883 method 1012.1). r jcb 1) r jleads 1) unit note tc1767 pg-lqfp-176-5 6.5 5.5 23 k/w
tc1767 electrical parameters data sheet 119 v1.4, 2012-07 5.4.2 package outline figure 36 pg-lqfp-176-5, plastic green low profile quad flat package you can find all of our packages, sorts of packing and others in our infineon internet page ?products?: http://www.infin eon.com/products .
tc1767 electrical parameters data sheet 120 v1.4, 2012-07 5.4.3 flash memory parameters the data retention time of the tc1767?s flash memory (i.e. the time after which stored data can still be retrieved) depends on the number of times the flash memory has been erased and programmed. table 27 flash parameters parameter symbol values unit note / test condition min. typ. max. program flash retention time, physical sector 1)2) 1) storage and inactive time included. 2) at average weighted junction temperature t j = 100 o c, or the retention time at average weighted temperature of t j = 110 o c is minimum 10 years, or the retention time at average weighted temperature of t j = 150 o c is minimum 0.7 years. t ret cc 20 ? ? years max. 1000 erase/program cycles program flash retention time logical sector 1)2) t retl cc 20 ? ? years max. 100 erase/program cycles data flash endurance per 32 kb sector n e cc 30 000 ? ? cycles max. data retention time 5years data flash endurance, eeprom emulation (4 16 kb) n e8 cc 120000 ? ? cycles max. data retention time 5years programming time per page 3) 3) in case the program verify feat ure detects weak bits, these bits will be programmed once more. the reprogramming takes additional 5 ms. t pr cc ? ? 5 ms ? program flash erase time per 256-kb sector t erp cc ? ? 5 s f cpu = 133 mhz data flash erase time for 2 x 32-kb sector t erd cc ? ? 2.5 s f cpu = 133 mhz wake-up time t wu cc ? ? 4000/ f cpu +180 s?
tc1767 electrical parameters data sheet 121 v1.4, 2012-07 5.4.4 quality declarations table 28 quality parameters parameter symbol values unit note / test condition min. typ. max. operation lifetime 1) 1) this lifetime refers only to the time when the device is powered on. t op ? ? 24000 hours ? 2) 3) 2) for worst-case temperature profile equivalent to: 2000 hours at t j = 150 o c 16000 hours at t j = 125 o c 6000 hours at t j = 110 o c 3) this 30000 hours worst-case temperature profile is also covered: 300 hours at t j = 150 o c 1000 hours at t j = 140 o c 1700 hours at t j = 130 o c 24000 hours at t j = 120 o c 3000 hours at t j = 110 o c esd susceptibility according to human body model (hbm) v hbm ? ? 2000 v conforming to jesd22-a114-b esd susceptibility of the lvds pins v hbm1 ?? 500v ? esd susceptibility according to charged device model (cdm) v cdm ? ? 500 v conforming to jesd22-c101-c moisture sensitivity level msl ? ? 3 ? conforming to jedec j-std-020c for 240c
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